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| [[Image:DAC_Emulator_Block.JPG|thumb|Functional block diagram of the DAC emulator.]] | | [[Image:DAC_Emulator_Block.JPG|thumb|Functional block diagram of the DAC emulator.]] |
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− | The block diagram is shown to the right, and each block is described on the [[Programming_the_FPGA#Emulator_.28D.29|FPGA programming page]]. | + | The block diagram is shown to the right, and each block is described on the [[Programming_the_FPGA#Emulator_.28D.29|FPGA programming page]]. Note that the repeated blocks (the 32 terminal registers) are not all drawn. Two or three are generally sufficient to illustrate connections (for example, does a line feed all 32, or are there 32 separate lines?). Ellipses are perfectly acceptable. |
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| == Enter the code monkey == | | == Enter the code monkey == |
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| :''See also: [http://en.wikipedia.org/wiki/Code_monkey code monkey]'' | | :''See also: [http://en.wikipedia.org/wiki/Code_monkey code monkey]'' |
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− | Now we lay down some actual code. | + | Now we lay down some actual code. First things first: comments! If you've ever done any programming, you know how wonderful comments are. If you've not done much coding, then remember that comments are not as pointless as they seem. Add descriptive comments or be murdered in your sleep 15 years from now by an irate engineer who has to decipher your legacy code. VHDL has no block comments, only line comments (the comment goes from the comment marker to the end of the line). The comment marker is a double dash with no spacing between them. Many development environments (for example Xilinx ISE) will auto-generate a large block of comments at the top of each file to be used to describe the file (who, what, where, when, why, how, and so on). |
| + | |
| + | Secondly are the libraries. These are like the include statements in C/C++. Honestly I forget which libraries have exactly what tools in them, but a standard block will cover mostly any design you work on: |
| + | |
| + | <code> |
| + | -- This standard block will cover you for most designs. |
| + | -- Some development environments will auto-generate library "use" statements that may or may not include this set |
| + | library IEEE; |
| + | use IEEE.STD_LOGIC_1164.ALL; |
| + | use IEEE.STD_LOGIC_ARITH.ALL; |
| + | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
| + | </code> |
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