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=== The block diagram ===
=== The block diagram ===
Having defined your block box, you need to fill in your black box.
Having defined your block box, you need to fill in your black box. But before doing that, we need to note the different between two types of logic:
* ''Combinational logic'' merely recombines lines into new lines. For example, signal Q may be the logical AND of signals A, B, and C. There is no reference to a clock in combinational logic.
* ''Sequential logic'' is any logic that makes use of a clock for latches, flip-flops, registers, or other devices. Sequential logic changes only when the clock changes. Often circuits are wired so that all sequential logic changes together, either on a ''falling edge'' of a clock or a ''rising edge'' of a clock. Advanced designs can change some components on a rising edge and other components on a falling edge, but this is significantly more difficult due to the tighter timing restrictions imposed.
A "good" design does its best to separate combinational and sequential logic. All combinational logic takes time; each gate has a delay associated with it. Highly complex combinational logic can take long enough to skew the timing of your circuit; some lines will clock in too late and will take effect on the following clock cycle, completely ruining your synchronization and causing sporadic or faulty behavior in your circuit. For this reason it is best to separate the two types of logic as best you can, although it is not always possible to fully separate them. Generally the sequential block will feed the combinational block, and the combinational block will loop back to the sequential block for any required feedback or recursion.
Bearing this in mind, you need to partition your design into functional blocks. Each functional block will be a new black box within the larger design, with two well-defined attributes: I/O pins and functionality. Sometimes these '''functional block diagrams''' will become layered, with a functional block in the top-most diagram having a functional block diagram describing its own internals. For complex designs, there can be many layers and many engineers, so that each engineer is only working on a small subset of the components so that the I/O ports and functionality must be precisely defined and followed so that integration of the components requires a minimum of component redesign. The functional block diagram shows the I/O ports of the overall design (if you have no inouts, it is conventional to put inputs on the left and outputs on the right at all times to clarify data flow), all blocks (with I/O ports labeled), and signals connecting each block as appropriate.
Notes:
* Since clock lines are required for most designs (every sequential block needs one), most engineers no longer write the world "clock" or even the abbreviation "CLK" on a block diagram. Instead it is understood that a clock line is represented by a small carat or divot on the side of the block (often placed in the top left corner of the block, but that is not a requirement).
* Many devices are general purpose, so giving a descriptive label to a pin would be pointless as the description will change depending on the application. A common shorthand for such blocks is to use "D" as the input signal and "Q" as the output signal. This is often seen on registers, multiplexers, flip-flops, etc.
=== Example: the block diagram ===
[[http://zeus.phys.uconn.edu/wiki/index.php?title=Image:DAC_Emulator_Block.JPG|thumb|Functional block diagram of the DAC emulator.]]
The block diagram is shown to the right, and each block is described on the [[http://zeus.phys.uconn.edu/wiki/index.php?title=Programming_the_FPGA#Emulator_.28D.29|FPGA programming page]].