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The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in [http://en.wikipedia.org/wiki/VHDL VHDL]. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in [http://en.wikipedia.org/wiki/VHDL VHDL]. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
''Open question:'' What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
== The DAC ==
== The DAC ==
* ''SDI'': Serial Data In (input), data input line
* ''SDI'': Serial Data In (input), data input line
* ''SDO'': Serial Data Out (output), data output line
* ''SDO'': Serial Data Out (output), data output line
Note that the input/output notations are for slave devices (such as the temperature sensor) but are reversed for master devices (such as the FPGA). Proper SPI protocol flips the I/O polarity of ''CE'' and ''SCLK'' and crosses the ''SDI'' and ''SDO'' lines so that ''SDI'' is an input on every device and ''SDO'' is always an output. To maintain simplicity in wiring conventions we are not using proper SPI protocol, but are calling the slave input/master output line ''SDI'' and the slave output/master input line ''SDO'' so that the SDI/O notations are proper for slaves. The maximum clock rate is no higher than 10MHz. The interface, having separate input and output lines, is full-duplex; in fact the temperature sensor is unable to function in half-duplex mode. Outputs from the temperature sensor change on rising edges of ''SCLK'', but inputs are latched on falling edges.
Note that the input/output notations are for slave devices (such as the temperature sensor) but are reversed for master devices (such as the FPGA). Proper SPI protocol flips the I/O polarity of ''CE'' and ''SCLK'' and crosses the ''SDI'' and ''SDO'' lines so that ''SDI'' is an input on every device and ''SDO'' is always an output. To maintain simplicity in wiring conventions we are not using proper SPI protocol, but are calling the slave input/master output line ''SDI'' and the slave output/master input line ''SDO'' so that the ''SDI/O'' notations are proper for slaves. The maximum clock rate is no higher than 10MHz. The interface, having separate input and output lines, is full-duplex; in fact the temperature sensor is unable to function in half-duplex mode. Outputs from the temperature sensor change on rising edges of ''SCLK'', but inputs are latched on falling edges.
There is only one write operation to the temperature sensor and that is used to direct the temperature sensor to enter power-down mode. We do not plan to use this mode, so the ''SDI'' input on the temperature sensor will be tied to ground.
A read operation occurs during a 16-cycle pulse of ''CE''. The first transmitted bit will be zero, followed by ten bits of temperature data (MSB first). The remaining five bits are copies of the final data bit. After ''CE'' goes low ''SDO'' goes into a high-Z state. Temperature data is given in degrees Celsius. The format is two's-complement with two decimal places; in essence it is standard two's-complement, then the result must be divide by four after converting to decimal.
=== Emulator ===
=== Emulator ===