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Line 33:
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no edit summary
| U || X || X || X || X || X || X || X || X
| U || X || X || X || X || X || X || X || X
|}
|}
VHDL Logic States
* U: uninitialized
* X: forcing unknown
* 0: forcing 0
* 1: forcing 1
* Z: high impedance
* W: weak unknown
* L: weak 0
* H: weak 1
* -: don't care