Changes

=== The FPGA ===

=== The FPGA ===

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic.  A currently open question is which size of FPGA to choose.  The total number of system gates is 50k, 200k, 400k, 700k, or 1400k.  The likely method of choosing the proper FPGA is to design the [http://en.wikipedia.org/wiki/Hardware_description_language HDL] and synthesize it, then decide on a model based on number of logic cells and I/O pins required by the synthesized HDL.

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic.  A currently open question is which size of FPGA to choose.  The total number of system gates is 50k, 200k, 400k, 700k, or 1400k.  The likely method of choosing the proper FPGA is to design the [http://en.wikipedia.org/wiki/Hardware_description_language HDL] and synthesize it, then decide on a model based on number of logic cells and I/O pins required by the synthesized HDL.