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The '''SiPM digital control board''' is the communication block for controlling the SiPMs. It provides the interface through which an external system can control or monitor the SiPMs.
== Responsibilities of the control board ==
The control board is responsible for providing a layer of interaction between the researchers running the experiments and the tagger microscope. The foremost responsibility of the control board is to allow the users to program the bias voltage (which controls the gain) of the SiPMs. It receives signals from an external PC and communicates that information to a DAC which controls the bias voltage. It also monitors itself and reports back to the PC certain statistics, such as voltage of the power lines (to ensure the chips and SiPMs are receiving the required voltages) and temperature of the control board and its immediate vicinity (to ensure that the electronics are not overheating).
== Flow of information ==
The hub of the control board, its "central nervous system", is an [http://en.wikipedia.org/wiki/FPGA FPGA]. All components on the board connect to the FPGA and it coordinates their interactions. Communication with the outside world (more specifically an external PC) occurs over Ethernet. Towards that end an Ethernet chip is included on the board and connected to the FPGA. The main purpose of the board is to control bias voltages, so a [http://en.wikipedia.org/wiki/Digital-to-analog_converter DAC] is attached to the board and connected to the FPGA. There are two monitoring devices so that the board can ensure that it is running properly: a temperature sensor and an [http://en.wikipedia.org/wiki/Analog-to-digital_converter ADC], both of which are connected to the FPGA.
== The components ==
There are five main components included on the digital control board, not counting interconnect wires, passive components, crystals, etc.
=== The FPGA ===
The FPGA is the hub of the digital control board. All components communicate through the FPGA and are controlled by the FPGA. The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA. The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this. The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. A currently open question is which size of FPGA to choose. The total number of system gates is 50k, 200k, 400k, 700k, or 1400k. The likely method of choosing the proper FPGA is to design the [http://en.wikipedia.org/wiki/Hardware_description_language HDL] and synthesize it, then decide on a model based on number of logic cells and I/O pins required by the synthesized HDL.
=== The Ethernet controller ===
After researching a variety of communication buses, including USB, I<sup>2</sup>C, FireWire, and various others, it was decided that the best choice would be [http://en.wikipedia.org/wiki/Ethernet Ethernet]. Ethernet is based on a multi-layer protocol, which each higher layer adding more advanced capabilities. Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. We have selected the Silicon Laboratories' CP2200/1 Ethernet controller. The CP2200 and CP2201 are the same chip with the differences lying (primarily) in packaging and I/O pin count. Likely the CP2201 (the smaller chip) will prove sufficient, as of June, 2007 that decision has not been finalized. The CP2200/1 supplied layers one and two automatically and can interface with the FPGA through a parallel bus described by the CP2200/1 data sheet.
=== The DAC ===
== Responsibilities of the control board ==
The control board is responsible for providing a layer of interaction between the researchers running the experiments and the tagger microscope. The foremost responsibility of the control board is to allow the users to program the bias voltage (which controls the gain) of the SiPMs. It receives signals from an external PC and communicates that information to a DAC which controls the bias voltage. It also monitors itself and reports back to the PC certain statistics, such as voltage of the power lines (to ensure the chips and SiPMs are receiving the required voltages) and temperature of the control board and its immediate vicinity (to ensure that the electronics are not overheating).
== Flow of information ==
The hub of the control board, its "central nervous system", is an [http://en.wikipedia.org/wiki/FPGA FPGA]. All components on the board connect to the FPGA and it coordinates their interactions. Communication with the outside world (more specifically an external PC) occurs over Ethernet. Towards that end an Ethernet chip is included on the board and connected to the FPGA. The main purpose of the board is to control bias voltages, so a [http://en.wikipedia.org/wiki/Digital-to-analog_converter DAC] is attached to the board and connected to the FPGA. There are two monitoring devices so that the board can ensure that it is running properly: a temperature sensor and an [http://en.wikipedia.org/wiki/Analog-to-digital_converter ADC], both of which are connected to the FPGA.
== The components ==
There are five main components included on the digital control board, not counting interconnect wires, passive components, crystals, etc.
=== The FPGA ===
The FPGA is the hub of the digital control board. All components communicate through the FPGA and are controlled by the FPGA. The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA. The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this. The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. A currently open question is which size of FPGA to choose. The total number of system gates is 50k, 200k, 400k, 700k, or 1400k. The likely method of choosing the proper FPGA is to design the [http://en.wikipedia.org/wiki/Hardware_description_language HDL] and synthesize it, then decide on a model based on number of logic cells and I/O pins required by the synthesized HDL.
=== The Ethernet controller ===
After researching a variety of communication buses, including USB, I<sup>2</sup>C, FireWire, and various others, it was decided that the best choice would be [http://en.wikipedia.org/wiki/Ethernet Ethernet]. Ethernet is based on a multi-layer protocol, which each higher layer adding more advanced capabilities. Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. We have selected the Silicon Laboratories' CP2200/1 Ethernet controller. The CP2200 and CP2201 are the same chip with the differences lying (primarily) in packaging and I/O pin count. Likely the CP2201 (the smaller chip) will prove sufficient, as of June, 2007 that decision has not been finalized. The CP2200/1 supplied layers one and two automatically and can interface with the FPGA through a parallel bus described by the CP2200/1 data sheet.
=== The DAC ===