VHDL tutorial

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Revision as of 19:45, 5 July 2007 by Krueger (talk | contribs)
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To be added: a tutorial on VHDL design with a design example (likely the DAC emulator). Also to be included: the VHDL resolution table:

VHDL Resolution Table
U X 0 1 Z W L H -
U U U U U U U U U U
X U X X X X X X X X
0 U X 0 X 0 0 0 0 X
1 U X X 1 1 1 1 1 X
Z U X 0 1 Z W L H X
W U X 0 1 W W W W X
L U X 0 1 L W L W X
H U X 0 1 H W W H X
- U X X X X X X X X

VHDL Logic States

  • U: uninitialized
  • X: forcing unknown
  • 0: forcing 0
  • 1: forcing 1
  • Z: high impedance
  • W: weak unknown
  • L: weak 0
  • H: weak 1
  • -: don't care