Difference between revisions of "FPGA Reset"

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:''See also [[Programming_the_Ethernet_Controller|Programming the Ethernet Controller]]'' for a survey of modules and general discussion of FPGA design approach.''
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= (00X) Reset Modules =
 
= (00X) Reset Modules =
  

Revision as of 00:07, 3 June 2008

See also Programming the Ethernet Controller for a survey of modules and general discussion of FPGA design approach.

(00X) Reset Modules

The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)

The control packets type bytes leading to states 00X pertaining to these reset modules are:

Packet Type Byte Effect on the FPGA
Type Hex Bin State Description
R 0x52 0101 0010 000 "Reset_hard" instruction
"R'" 0xD2 1101 0010 001 Essentially an 'R' byte with '1' in the MSB instructing the FPGA to enter a reset cycle of the soft kind.


Programming Details

Ports

  • Clk: [in] clock


Reset Signals

  • Rst: [in] asynchronous reset
  • Eth_iRst: [inout] EC active-low reset pin
  • Eth_iINT: [in] EC active-low interrupt signal


State Register Control Lines

  • state_En: [out] state register enable (write) signal
  • state_D: [out] (3-bit) state register input
  • state_Q: [in] (3-bit) state register output


MAC Address Register Control Lines

  • MACregs_En: [out] register enable (write) signal
  • MACregs_A: [out] byte address (4-bit)
  • MACregs_D: [out] 8-bit input value


Transceiver Control Lines

  • TxRx_Go: [out] "Go" signal to read/write an EC control register byte
  • TxRx_Aout: [out] EC control register address (8-bit)
  • TxRx_Dout: [out] EC control register write value
  • TxRx_RiW: [out] active-high read, active-low write flag
  • TxRx_Din: [in] EC control register return value
  • TxRx_Done: [in] "Done" signal from Transceiver.
  • dbShort: [in] debug signal to bypass EC reset waiting periods