Difference between revisions of "FPGA Reader"
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| + | :''See also [[Programming_the_Ethernet_controller|Programming the Ethernet Controller]]'' for a survey of modules and a general discussion of FPGA design approach.'' | ||
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= (011) Read Packet = | = (011) Read Packet = | ||
| − | This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the packet type is invalid. Otherwise it will yield control to the module relevant to the packet type. | + | [[Image:ReaderProcess.png|thumb|236px|Process flow of the Reader module. "my_Loc" represents either the constant 8-bit value hard-coded into the slot to which the digital board is attached or the wild card: 0xFF]] |
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| + | This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the [[Ethernet_packets|packet type]] is invalid. Otherwise it will yield control to the module relevant to the packet type. This selection is diagrammed in the adjacent figure. | ||
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| + | As implied in the diagram, packet types R and Q (Reset and Query respectively) do no carry any data for the FPGA: their role is to order reset or request feedback from the sensor chips. Soft Reset and Programmer, on the other hand require certain reset/configuration data and DAC voltage values respectively, so these packets are kept. (It becomes the responsibility of these modules to dismiss these packets when finished.) | ||
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| + | Instead of implementing MAC address filtering, necessitating a lookup table of MAC address to Energy channel group, it was seen as more convenient to include an 8-bit bus into the slots for the digital boards, each hard-wired to hold a unique location value. Knowing the number of energy channels controlled on each board, the packet addressing is straightforward. Packet filtering is also made easy for the Reader: it requires a simple 8-bit comparison between the hard-coded value and that in the first byte of the packet payload. | ||
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| + | == Programming Details == | ||
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| + | [[Image:PacketFormat.png|thumb|325px|Custom format of the packets exchanged between digital control boards and the PC.]] | ||
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| + | The module is implemented as a counter of bytes read with the auto-read interface of the Ethernet Controller chip (EC) starting from the beginning of the header. ''AutoRd'' module is instantiated and is pulsed on each counter click. Upon reading the 15th, the location is checked for match to the board slot's hardwired location (''LocStamp'' port listed below). Upon the 16th byte, the packet type is checked. Packet rejection (skipping in the receive buffer) if performed by writing "00000010" to RXCN (0x11) control register. (See the CP220x manual for more information.) ''wrToAddr'' module is instantiated and is pulsed by the Discard signal which may be turned high at any point of the selection process. | ||
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| + | Note that after stepping through the 14 bytes of the packet header and reading the first two bytes of the payload it leaves the receive (Rx) buffer pointer on the 17th byte (or 3rd byte of payload). The Soft Reset and Programmer modules can continue reading with the auto-read interface to access the data relevant to them. | ||
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| − | + | === Ports === | |
| − | + | * ''Clk'': [in] clock | |
| − | + | * ''Rst'': [in] asynchronous reset | |
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| − | + | [[FPGA_Registers#State_Register|State Register]] Control Lines | |
| + | * ''state_En'': [out] state register enable (write) signal | ||
| + | * ''state_D'': [out] (3-bit) state register input | ||
| + | * ''state_Q'': [in] (3-bit) state register output | ||
| − | + | * ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot | |
| − | * '' | ||
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| − | + | [[FPGA_Transceiver|Transceiver]] Control Lines | |
| − | * '' | + | * ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte |
| − | + | * ''TxRx_RiW'': [out] active-high read, active-low write flag | |
| − | + | * ''TxRx_Aout'': [out] EC control register address (8-bit) | |
| − | + | * ''TxRx_Dout'': [out] EC control register write value | |
| − | + | * ''TxRx_Din'': [in] EC control register return value | |
| − | + | * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]] | |
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Latest revision as of 00:15, 3 June 2008
- See also Programming the Ethernet Controller for a survey of modules and a general discussion of FPGA design approach.
(011) Read Packet
This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the Idler (010) if the packet is not addressed to its location or the packet type is invalid. Otherwise it will yield control to the module relevant to the packet type. This selection is diagrammed in the adjacent figure.
As implied in the diagram, packet types R and Q (Reset and Query respectively) do no carry any data for the FPGA: their role is to order reset or request feedback from the sensor chips. Soft Reset and Programmer, on the other hand require certain reset/configuration data and DAC voltage values respectively, so these packets are kept. (It becomes the responsibility of these modules to dismiss these packets when finished.)
Instead of implementing MAC address filtering, necessitating a lookup table of MAC address to Energy channel group, it was seen as more convenient to include an 8-bit bus into the slots for the digital boards, each hard-wired to hold a unique location value. Knowing the number of energy channels controlled on each board, the packet addressing is straightforward. Packet filtering is also made easy for the Reader: it requires a simple 8-bit comparison between the hard-coded value and that in the first byte of the packet payload.
Programming Details
The module is implemented as a counter of bytes read with the auto-read interface of the Ethernet Controller chip (EC) starting from the beginning of the header. AutoRd module is instantiated and is pulsed on each counter click. Upon reading the 15th, the location is checked for match to the board slot's hardwired location (LocStamp port listed below). Upon the 16th byte, the packet type is checked. Packet rejection (skipping in the receive buffer) if performed by writing "00000010" to RXCN (0x11) control register. (See the CP220x manual for more information.) wrToAddr module is instantiated and is pulsed by the Discard signal which may be turned high at any point of the selection process.
Note that after stepping through the 14 bytes of the packet header and reading the first two bytes of the payload it leaves the receive (Rx) buffer pointer on the 17th byte (or 3rd byte of payload). The Soft Reset and Programmer modules can continue reading with the auto-read interface to access the data relevant to them.
Ports
- Clk: [in] clock
- Rst: [in] asynchronous reset
State Register Control Lines
- state_En: [out] state register enable (write) signal
- state_D: [out] (3-bit) state register input
- state_Q: [in] (3-bit) state register output
- LocStamp: [in] 8-bit board location value as hard-coded into the board's slot
Transceiver Control Lines
- TxRx_Go: [out] "Go" signal to read/write an EC control register byte
- TxRx_RiW: [out] active-high read, active-low write flag
- TxRx_Aout: [out] EC control register address (8-bit)
- TxRx_Dout: [out] EC control register write value
- TxRx_Din: [in] EC control register return value
- TxRx_Done: [in] "Done" signal from Transceiver