Difference between revisions of "Programming the Ethernet controller"

From UConn PAN
Jump to navigation Jump to search
Line 31: Line 31:
 
** inouts
 
** inouts
 
*** ''AD'': 8-bit address and data bus
 
*** ''AD'': 8-bit address and data bus
 +
* '''state register'''
 +
** A three-bit register to store the current state.
 +
** inputs
 +
*** ''Clk'': clock
 +
*** ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state)
 +
*** ''En'': write enable
 +
*** ''D'': three-bit data-in bus
 +
** outputs
 +
*** ''Q'': three-bit data-out bus
  
 
=== (000) Reset Cycle ===
 
=== (000) Reset Cycle ===

Revision as of 15:22, 19 July 2007

Interface

See also: Ethernet packets
See also: Ethernet state diagram

Emulator

Controller

  • transceiver
    • This block provides a level of abstraction between the precise CP2200/1 interface and a generalized interface seen by the internal blocks of the FPGA. It takes information on the next transfer to carry out and returns information on the last transfer completed. It has a pulse signal to begin a transfer and a pulse signal to notify of a completed transfer. This eliminates a need for the internal workings of the FPGA to be aware of the timing of the interface; it simply begins a transfer and waits for notification of the transfer's completion.
    • inputs
      • CLK: clock
      • /Rst: asynchronous, active-low reset
      • Go: pulse to begin a transmission
      • R/W_in: read/write toggle: active-high read, active-low write
      • A_in: 8-bit bus for address to read to/write from
      • D_in: 8-bit bus for data to write; ignored during a read
    • outputs to internals
      • Done: pulse to signal completion of a transmission
      • R/W_out: read/write flag: active-high read, active-low write
      • A_out: 8-bit bus for address of last read/write
      • D_out: 8-bit bus for data of last read; internal systems should ignore for a write
    • outputs to CP2200/1
      • /CS: active-low chip select
      • MotEn: Motorola/Intel format toggle: active-high Motorola, active-low Intel
      • MuxEn: Multiplexed flag; not used for CP2201
      • ALE: ALE strobe
      • /Wr: Active-low write flag
      • /Rd: Active-low read flag
    • inouts
      • AD: 8-bit address and data bus
  • state register
    • A three-bit register to store the current state.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset to zero the register (puts system into reset state)
      • En: write enable
      • D: three-bit data-in bus
    • outputs
      • Q: three-bit data-out bus

(000) Reset Cycle

inputs

  • Clk: clock
  • /Rst: asynchronous, active-low reset
  • State: 3-bit state value
  • D_En: DAC enable, assume held high/low by previous block
  • A_En: ADC enable, assume held high/low by previous block
  • E_En: Ethernet enable, assume held high/low by previous block

internal signals

  • S_En: state enable, S_En <= not (St(2) or St(1) or St(0))
  • Go: when S_En goes high Go pulses for one cycle
  • D_Go: DAC reset go pulse, D_Go <= Go and D_En
  • A_Go: ADC reset go pulse, A_Go <= Go and A_En
  • E_Go: Ethernet reset go pulse, E_Go <= Go and E_En

blocks

  • DAC Reset
    • Resets and initializes the DAC.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • D_Go: go pulse to begin reset/initialization process
    • outputs
      • - All DAC reset/initialization control lines -
      • D_Done: goes high when reset/initialization process is complete, falls on D_Go pulse
  • ADC Reset
    • Resets and initializes the ADC.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • A_Go: go pulse to begin reset/initialization process
    • outputs
      • - All ADC reset/initialization control lines -
      • A_Done: goes high when reset/initialization process is complete, falls on A_Go pulse
  • Ethernet Reset
    • Resets and initializes the Ethernet controller.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • E_Go: go pulse to begin reset/initialization process
    • outputs
      • - All Ethernet reset/initialization control lines -
      • E_Done: goes high when reset/initialization process is complete, falls on E_Go pulse
  • Coordinator
    • Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
    • inputs
      • Clk: clock
      • /Rst: asynchronous, active-low reset
      • D_En: high when DAC is to be reset
      • D_Done: high when DAC is done resetting
      • A_En: high when ADC is to be reset
      • A_Done: high when ADC is done resetting
      • E_En: high when Ethernet controller is to be reset
      • E_Done: high when Ethernet controller is done resetting
    • internal signals
      • Flag <= (D_Done or not D_En) and (A_Done or not A_En) and (E_Done or not E_En)
    • outputs
      • Done: when Flag goes high, Done pulses for one cycle; connects to state register as an enable
      • New_St: new state to be written to the state register; goes to 001 while Done is high

(001) Transmit "I"

(010) Idle

inputs:

  • Clk: clock
  • /Rst: asynchronous, active-low reset
  • State: 3-bit state value
  • TxRx_A: 8-bit address from transceiver
  • TxRx_D: 8-bit data from transceiver
  • TxRx_Done: pulse from transceiver to signal transfer complete

internal signals

  • S_En: state enable, S_En <= not St(2) and St(1) and not St(0)
  • Go: when S_En goes high Go pulses for one cycle

blocks

  • Fetcher
    • Reads register 0x76 (INT0RD) by sending a read request to the transceiver
    • inputs
      • F_Go: pulse to start request, F_Go <= Go or Loop
    • outputs
      • TxRx_Go: Go line on transceiver
      • TxRx_R/W: R/W line on transceiver, tied high (read)
      • TxRx_A: A_in bus on transceiver, tied to 0x76 (0111 0110)
        • Note: D_in on transceiver is not used; assume this line defaults to zero
  • Looper
    • Switch to determine if this state should loop on itself or continue to the next state.
    • inputs
      • S_En: state enable
      • TxRx_Done: Done pulse from transceiver
      • TxRx_Data: D_out bus from transceiver
    • outputs
      • Loop: pulse to repeat fetch cycle; Loop <= S_En and TxRx_Done and TxRx_Data(6)
      • Done: pulse to finish state; connects to state counter as an enable in order to increment the state to 011; Done <= S_En and TxRx_Done and not TxRx_Data(6)

(011) Read Packet

(100) Poll Status

(101) Transmit "S"

(110) Program DAC

(111) Transmit "D"