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[[Image:Spartan.jpg|right]]

[[Image:Spartan.jpg|right]]

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. The code for the FPGA has been written in [[VHDL_tutorial|VHDL]] and is in the final stages of debugging. The question as to which size of FPGA to choose from the available 50k-1400k may be settled, as the current design implementation fits within the 50k unit.  

The FPGA is the hub of the digital control board.  All components communicate through the FPGA and are controlled by the FPGA.  The chip we plan to use is the [http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3a_fpgas/index.htm Xilinx Spartan-3A] FPGA.  The Spartan line of FPGAs are low-cost chips well-suited for small designs such as this.  The 3A model is optimized for I/O and includes a large number of I/O pins, which will be beneficial considering the amount of interconnect relative to the amount of logic. The code for the FPGA, written in [[VHDL_tutorial|VHDL]], is complete. Remaining tweaks are subject to the use experience during beam tests and any other field experience.

The code fits within the smallest version of the chip in terms of gates and pins, which greatly simplifies the board assembly and reduces cost. The design did, however rely on Xilinx ''primitives'' (instantiation of device-specific resources) for large registers required by the code.

The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].

The data sheet, user guide, configuration guide, and other documentation regarding the FPGA can be downloaded from the [http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Spartan-3A Xilinx website].

Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and SPI (bus for ADC and Temperature sensor) controller modules when access to these chips is required. Please see the relevant pages from the following list.

Much of the FPGA programming is concerned with the complex operations of the Ethernet controller chip [[#The Ethernet controller|CP2200/1 discussed below]]. This core interacts with the DAC and the SPI-based ADC and Temperature sensor when access to these chips is required. Please see the relevant pages from the following list.

* [[Programming the Ethernet controller|Programming the Ethernet controller (core of FPGA design)]]

* [[Programming the Ethernet controller|Programming the Ethernet controller (core of FPGA design)]]

** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.

** [[Reset and Initialization]] - discussion of reset/initialization needs of our chips.

* [[Programming the DAC|Programming the DAC controller]]

* [[Programming the DAC|Programming the DAC controller]]

=== The Ethernet controller ===

=== The Ethernet controller ===

After researching a variety of communication buses, including USB, I²C, FireWire, and various others, it was decided that the best choice would be Ethernet.  Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. In addition, due to the wide availability of Ethernet hubs/switches, Ethernet will help to minimize the number of wires that must be run between the control board array and the main computer.  

After researching a variety of communication buses, including USB, I²C, FireWire, and various others, it was decided that the best choice would be Ethernet.  Ethernet is based on a multi-layer protocol, with each higher layer adding more advanced capabilities.  Only layers one and two are necessary for our purposes, being a local network not connected to a true internet. The wide availability of Ethernet products is a major advantage of this choice of communication scheme.

We have selected the Silicon Laboratories CP2200/1 Ethernet controller.  The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA has been designed around this chip.

We have selected the Silicon Laboratories CP2200/1 Ethernet controller.  The two variants of the chip differ (primarily) in packaging and I/O pin count: the CP2201 requires a ''Multiplexed'' Intel Bus interface, saving many pins. The FPGA firmware has been designed around this chip.

The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].

The data sheet and other information regarding the Ethernet controller can be downloaded from the [http://www.silabs.com/tgwWebApp/public/web_content/products/Microcontrollers/Interface/en/CP220x.htm Silicon Laboratories website].

=== The DAC ===

=== The DAC ===

The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs.  For this purpose a DAC is required.  The current design of the tagger microscope calls for 16 SiPMs per electronics card, however designs of up to 24 SiPMs per electronics card are being considered. Various designs were studied, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535.  It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels. As there are so many channels built in to this system, the tagger may be slightly restructured so as to include up to 32 SiPMs per board instead of 16 per board.  This DAC defines its own serial interface for communication with the FPGA.

The purpose of the control board is to allow remotely programmable bias voltages for the SiPMs.  For this purpose a DAC is required.  The current design of the tagger microscope calls for 25 or 30 SiPMs per amplifier board (to read out an entire 5x5 or 5x6 scintillating fiber bundle.) Various designs were studied, but based on availability of components in the 50V range (DACs and op-amps primarily) the most suitable choice found was the Analog Devices' AD5535.  It can go up to 200V with a resolution of 14 bit (roughly 12mV at 200V scale, roughly 3mV at a 50V scale) on 32 channels. The chip defines its own serial interface for communication with the FPGA.

The data sheet and other information regarding the DAC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html Analog Devices website].

The data sheet and other information regarding the DAC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html Analog Devices website].

=== The ADC ===

=== The ADC ===

[[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]

[[Image:SPI-like bus.JPG|thumb|SPI-like bus topology]]

In order to monitor the voltage levels of the power lines and possibly some DAC channels, an ADC is to be included in the design. The Analog Devices' AD7928 is an eight-channel ADC. Based on the selection of components there are six necessary power lines and two necessary grounds, so the AD7928 is capable of monitoring the entire system if need be.  It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.

In order to monitor the voltage levels of the power lines, an ADC was included in the design. Additional important uses of the chip is monitoring of a DAC channel for online calibration and temperature measurements of the DAC (integrated diode provided) and the amplifier board via its thermistor.

 

The device chosen is the Analog Devices' AD7928 - an 8-channel ADC. It uses a serial protocol that is compatible with the SPI bus to communicate with the FPGA.

The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].

The data sheet and other information regarding the ADC can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7928%2C00.html Analog Devices website].

=== Temperature sensor ===

=== Temperature sensor ===

In order to monitor the ambient temperature, a temperature sensor is to be included in the design.  The Analog Devices' AD7314 has ten-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.

In order to monitor the ambient temperature, a temperature sensor is to be included in the design.  The Analog Devices' AD7314 has 10-bit resolution on temperature and is compatible with the SPI bus for communication with the FPGA.

The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].

The data sheet and other information regarding the temperature sensor can be downloaded from the [http://www.analog.com/en/prod/0%2C2877%2CAD7314%2C00.html Analog Devices website].