Physical Setup

Use the red Xilinx USB cable box to connect the digital control board to the computer.
The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Open Xilinx ISE Project Manager
In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
Select uParam within FPGA_ctrl.
To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
- This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
The maximum gainmode value can be changed similarly.
Save the file.
There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.

Now that the program has been changed and saved, open the Xilinx IMPACT program.
Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
Open fpga.ipf
There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
- EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
- FPGA on right, volatile and forgets its programming at every powerdown
Make sure that the digital board has power.
Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
The following settings should be used when creating the PROM
- Xilinx flash/prom
- PROM family platform flash
- Device xcf01s [1M]. Add if not already there.
- Output file name: fpga
- Save to /TotalTest
- Format mcs
- Don't add non-config data.
- Generate
Switch back to the boundary scan tab.
Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.