Latest revision as of 21:13, 6 January 2014

Current Guide to Flashing the Final Production FPGAs

Physical Setup

Use the red Xilinx USB cable box to connect the digital control board to the computer
When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Flashing the Program

Open the Project Navigator
1. On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
If the project doesn't load automatically, load the project file Device.xise
1. Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
2. FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
Edit any source files using Vim outside of the Xilinx software
Right click in the bottom left window on Configure Test Device and select "Rerun All"
1. This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
Run Generate Target PROM/ACE File
Run Manage Configuration Project (iMPACT)
1. This will open up the iMPACT program
2. Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
3. In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
4. TDI should connect to xcf01s_vo20 with the file device.mcs underneath
5. The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
In iMPACT in the top left window click on Create PROM File
1. This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
2. In the window titled "iMPACT Processes" run Generate File
3. When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
Click on Program in the iMPACT Processes window
1. This should erase any previous programming and flash the new program onto the FPGA

Igor's Guide to Flashing the First Prototype FPGA

Physical Setup

Use the red Xilinx USB cable box to connect the digital control board to the computer.
The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Editing the uParam program

Open Xilinx ISE Project Manager
In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
Select uParam within FPGA_ctrl.
To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
- This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
The maximum gainmode value can be changed similarly.
Save the file.
There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.

Flashing the program

Now that the program has been changed and saved, open the Xilinx IMPACT program.
Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
Open fpga.ipf
There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
- EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
- FPGA on right, volatile and forgets its programming at every powerdown
Make sure that the digital board has power.
Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
The following settings should be used when creating the PROM
- Xilinx flash/prom
- PROM family platform flash
- Device xcf01s [1M]. Add if not already there.
- Output file name: fpga
- Save to /TotalTest
- Format mcs
- Don't add non-config data.
- Generate
Switch back to the boundary scan tab.
Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.

Difference between revisions of "Programming the FPGA"

Latest revision as of 21:13, 6 January 2014

Contents

Current Guide to Flashing the Final Production FPGAs

Physical Setup

Xilinx Software

Flashing the Program

Igor's Guide to Flashing the First Prototype FPGA

Physical Setup

Xilinx Software

Editing the uParam program

Flashing the program

Navigation menu

Search

@@ Line 1: / Line 1: @@
-[[Image:Spartan.jpg|right]]
+= Current Guide to Flashing the Final Production FPGAs =
+==Physical Setup ==
+*Use the [http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm red Xilinx USB cable box] to connect the digital control board to the computer
+*When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
+*When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming
-The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it.  This article discusses the programming of the FPGA.  All code is written in [[VHDL_tutorial|VHDL]].  For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
+== Xilinx Software ==
+We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
-== Open questions ==
+=== Flashing the Program ===
+#Open the Project Navigator
+##On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
+#If the project doesn't load automatically, load the project file Device.xise
+##Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
+##FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
+#Edit any source files using Vim outside of the Xilinx software
+#Right click in the bottom left window on Configure Test Device and select "Rerun All"
+##This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
+#Run Generate Target PROM/ACE File
+#Run Manage Configuration Project (iMPACT)
+##This will open up the iMPACT program
+##Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
+##In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
+##TDI should connect to xcf01s_vo20 with the file device.mcs underneath
+##The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
+#In iMPACT in the top left window click on Create PROM File
+##This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
+##In the window titled "iMPACT Processes" run Generate File
+##When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
+#Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
+#Click on Program in the iMPACT Processes window
+##This should erase any previous programming and flash the new program onto the FPGA
-Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
+= Igor's Guide to Flashing the First Prototype FPGA =
-* What is the clock speed of the FPGA?  Timing constraints must be taken into account to link the multiple blocks.
+== Physical Setup ==
-* Current designs (11 July, 2007) account for normal activity.  Need to design modules/logic for startup and initialization of each component.  This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.
+*Use the red Xilinx USB cable box to connect the digital control board to the computer.
-* Do the parts work on falling or rising edges of the clock?  Most VHDL designs are currently on rising edges, but this can be easily corrected.
+*The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
-* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
+*2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
-== Component code ==
+== Xilinx Software ==
-* [[Programming the DAC]]
+We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
-* [[Programming the temperature sensor]]
-* [[Programming the ADC]]
-== The ADC ==
+=== Editing the uParam program ===
+*Open Xilinx ISE Project Manager
+*In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
+*Select uParam within FPGA_ctrl.
+*To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
+**This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
+*The maximum gainmode value can be changed similarly.
+*Save the file.
+*There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
-The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip here].
+=== Flashing the program ===
-=== Interface (A) ===
+*Now that the program has been changed and saved, open the Xilinx IMPACT program.
+*Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
-The AD7928 ADC has several features that we do not need: the shadow/sequencer and the multiple power modes.  They could be useful for more advanced or efficient functioning of the system, but are not needed.  Thus we will simplify the interface by turning these features off and running the ADC is the most basic mode.
+*Open fpga.ipf
+*There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
-The ADC has a four-wire interface that is compatible with the SPI bus protocol.  The four lines are:
+**EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
-* ''/CS'': Active-low chip select.  This line is high when the ADC is idle and goes low for 16 cycles during a conversation.  As this is active-low and the only other chip on the bus (the temperature sensor) has an active-high chip select line, it is possible to use a single chip select.  That would cause one or the other chip to always be running, which would be more information than we need or than we can send across Ethernet, but it is a possible design decision.
+**FPGA on right, volatile and forgets its programming at every powerdown
-* ''SCLK'': A serial clock.
+*Make sure that the digital board has power.
-* ''D_out'': Serial data out line, for communications from the ADC to the FPGA.  This line idles in high-Z.
+*Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
-* ''D_in'': Serial data in line, for communications from the FPGA to the ADC.
+*The following settings should be used when creating the PROM
+**Xilinx flash/prom
-On startup the ADC requires two "dummy" conversation that write all ones to the ADC and read garbage data from the ADC.
+**PROM family platform flash
+**Device xcf01s [1M]. Add if not already there.
-A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC.  The 12-bit control register has the following format:
+**Output file name: fpga
+**Save to /TotalTest
-{| align="center" cellpadding="1" border="1" cellspacing="1"
+**Format mcs
-|
+**Don't add non-config data.
-{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
+**Generate
-|- style="font-size:smaller; height:10px"
+*Switch back to the boundary scan tab.
-| style="width:8.33%" |11 || style="width:8.33%" |10 || style="width:8.33%" |09 || style="width:8.33%" |08 || style="width:8.33%" |07 || style="width:8.33%" |06 || style="width:8.33%" |05 || style="width:8.33%" |04 || style="width:8.33%" |03 || style="width:8.33%" |02 || style="width:8.33%" |01 || style="width:8.33%" |00
+*Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.
-|-
-| Write || Seq || DC || Addr<sub>2</sub> || Addr<sub>1</sub> || Addr<sub>0</sub> || Pow<sub>1</sub> || Pow<sub>0</sub> || Shadow || DC || Range || Coding
-|}
-|}
-The sections of the control register are:
-* Write:
-** if 0, do not update the remaining 11 bits of the control register
-** if 1, write new data to the control register
-* Seq: used for a feature we don't need: set to zero
-* DC: don't care
-* Addr(2:0): 3-bit address of channel to report on during next conversation
-* Pow(1:0): used for changing power modes: set to "11"
-* Shadow: used for a feature we don't need: set to zero
-* DC: don't care
-* Range: set to zero
-** if 0, analog input range is 0 to 2*V<sub>Ref</sub>
-** if 1, analog input range is 0 to V<sub>Reg</sub>
-* Coding: set to zero
-** if 0, output is twos-complement
-** if 1, output is binary-coded decimal
-Thus a conversation to read the voltage only (and not update the control register would look like
-{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
-| style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X
-|}
-and a conversation to set up a read on channel A(2:0) would look like
-{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
-| style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
-|}
-where an X is a don't-care state.  Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved.  The don't-care states in bits 9 and 2 we can set to zero.
-The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation.  We are going to use twos-complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.
-The control interface to the FPGA core will be:
-* ''Clk'': input: Clock line
-* ''Rst'': input: Asynchronous, active-low reset line
-* ''Go'': input: Pulse to begin transmission
-* ''Wr'': input: Flag whether or not to write new data to control register
-* ''A(2:0)'': input: Address to write to control register
-* ''C(2:0)'': output: Address of data coming from ADC
-* ''D(11:0)'': output: Data from ADC
-* ''Done'': output: Flag to tell core that new data is ready
-=== Emulator (A) ===
-[[Image:ADC Emulator Block.JPG|thumb|ADC emulator functional block diagram]]
-The functional block diagram for the emulator is shown to the right.  The blocks are:
-* '''shift in 16'''
-** This block is a 16-bit shift-in register with asynchronous, active-low reset and shift enable.  Custom outputs select the write bit and the data bits from the input string.  This register is designed to shift all 16 cycles of a transfer, but only make use of the first 12 bits of the input.
-** inputs
-*** ''CLK'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''En'': shift enable
-*** ''D'': data in line
-** outputs
-*** ''Q_W'': the write bit from the input string
-*** ''Q_D'': the 11 data bits from the input string
-* '''control reg'''
-** This block is an 11-bit register with asynchronous, active-low reset and a clock enable line.
-** inputs
-*** ''CLK'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''En'': read enable
-*** ''D'': data in
-** outputs
-*** ''Q'': data out
-* '''3-to-8 demux'''
-** This block is a 3-to-8 demultiplexer.
-** inputs
-*** ''D'': data to be demuxed
-*** ''S'': 3-bit select
-** outputs
-*** ''Q'': 8-bit output
-* '''error flag'''
-** This block generates a flag to ensure that data in the control register is in the right format (to help verify synchronization).  The format is: d00ddd110000, where a "d" is a don't-care state (0 or 1).
-** inputs
-*** ''D'': data in
-** outputs
-*** ''Err'': active-high error flag
-* '''shift out 15'''
-** This block is a 15-bit shift-out register with asynchronous, active-low reset and a shift/load toggle.  Custom inputs load the address (MSB first) as the first 3 bits and the data as the last 12 bits.  Idle output is a zero.
-** inputs
-*** ''CLK'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
-*** ''D'': data in
-*** ''A'': address in
-** outputs
-*** ''Q'': data out
-=== Controller (A) ===
-[[Image:ADC Controller Block.JPG|thumb|ADC controller functional block diagram]]
-The functional block diagram for the controller is shown to the right.  The blocks are:
-* '''counter'''
-** This block is a 5-bit counter.  It counts out 17 cycles: from the idle state, a pulse on the Go line begins a count of 16 cycles (during which time CS is low), then on the 17th cycle re-enters the idle state to await another pulse on Go.  The Go line is ignored during a 17-cycle run.
-** inputs
-*** ''CLK'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''Go'': pulse to leave idle state
-** outputs
-*** ''CS'': active-low chip select
-* '''delayer'''
-** This block is a single-cycle signal delayer.
-** inputs
-*** ''CLK'': clock
-*** ''D'': signal to be delayed
-** outputs
-*** ''Q'': delayed signal
-* '''shift out 12'''
-** This block is a 12-bit shift-out register with asynchronous, active-low reset and a shift/load toggle.  Custom inputs load the write bit and address bits, then fill in the remaining bits (W00AAA110000).  The register drags a trailing zero.  The output idles at zero when output is not enabled.
-** inputs
-*** ''CLK'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
-*** ''D_W'': write bit input
-*** ''D_A'': address bits input
-** outputs
-*** ''Q'': serial output
-* '''shift in 15'''
-** This block is a 15-bit shift-in register with asynchronous, active-low reset and shift enable.  Custom outputs select the address bits and data bits.
-** inputs
-*** ''CLK'': clock
-*** ''Rst'': asynchronous, active-low reset
-*** ''Sh'': shift enable
-*** ''D'': data in
-** outputs
-*** ''A'': address out
-*** ''Q'': data out
-== Ethernet controller ==
-=== Interface (E) ===
-:''See also: [[Ethernet packets]]''
-=== Emulator (E) ===
-=== Controller (E) ===
-== Reset and Initialization ==
-On start-up the FPGA must reset and initialize each component; especially the Ethernet controller.  Functionality will also be supplied to [[Ethernet_packets#The_reset_cycle|reset the system on a command from the PC]].
-=== The DAC ===
-The AD5535 DAC has an active-low reset pin.  Pulling that pin low will reset the DAC, zeroing all channels.
-=== The temperature sensor ===
-The AD7314 temperature sensor does not have a reset function.  It self-initializes on powering up.
-=== The ADC ===
-The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up.  The reset procedure is to hold the ''D<sub>in</sub>'' line high while performing two dummy conversions.  During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA.  It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.
-=== The Ethernet controller ===
-The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization").  The main points of the process will be covered here.
-* The first step is to wait for the reset pin to rise.  No flag will be raised upon the completion of this step other than the reset pin (which is an input to the CP2200/1) being high.
-* The second step is to wait for Oscillator Initialization to complete.  Completion of this will be signaled by an interrupt request signal.
-* The third step is to wait for Self Initialization to complete.  Completion of this will also be signaled by an interrupt request signal.
-* At this point all interrupts will be enabled.  Any interrupts which the FPGA will not handle should be disabled now.
-* The physical layer must be initialized, which is itself a multi-step process.
-** See section 15.7 "Initializing the Physical Layer"
-** If auto-negotiation is to be used see section 15.2 "Auto-Negotiation Synchronization."
-* Enable the Link, Act, or Activity/Link LED(s).
-* The MAC must now be initialized, another multi-step subprocess.
-** See section 14.1 "Initializing the MAC."
-* The receive filter must now be configured.
-** See section 12.4 "Initializing the Receive Buffer, Filter and Hash Table."
-* The CP2200/1 is now ready for regular operation.
-This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing the board and the PC are unable to communicate.