Difference between revisions of "Programming the FPGA"

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[[Image:Spartan.jpg|right]]
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= Current Guide to Flashing the Final Production FPGAs =
 +
==Physical Setup ==
 +
*Use the [http://www.xilinx.com/products/boards-and-kits/HW-USB-II-G.htm red Xilinx USB cable box] to connect the digital control board to the computer
 +
*When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
 +
*When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming
  
−
The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it.  This article discusses the programming of the FPGA.  All code is written in [[VHDL_tutorial|VHDL]].  For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.
+
== Xilinx Software ==
 +
We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
  
−
== Open questions ==
+
=== Flashing the Program ===
 +
#Open the Project Navigator
 +
##On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
 +
#If the project doesn't load automatically, load the project file Device.xise
 +
##Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
 +
##FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
 +
#Edit any source files using Vim outside of the Xilinx software
 +
#Right click in the bottom left window on Configure Test Device and select "Rerun All"
 +
##This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
 +
#Run Generate Target PROM/ACE File
 +
#Run Manage Configuration Project (iMPACT)
 +
##This will open up the iMPACT program
 +
##Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
 +
##In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
 +
##TDI should connect to xcf01s_vo20 with the file device.mcs underneath
 +
##The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
 +
#In iMPACT in the top left window click on Create PROM File
 +
##This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
 +
##In the window titled "iMPACT Processes" run Generate File
 +
##When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
 +
#Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
 +
#Click on Program in the iMPACT Processes window
 +
##This should erase any previous programming and flash the new program onto the FPGA
  
−
Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.
+
= Igor's Guide to Flashing the First Prototype FPGA =
−
* What is the clock speed of the FPGA?  Timing constraints must be taken into account to link the multiple blocks.
+
== Physical Setup ==
−
* Current designs (11 July, 2007) account for normal activity.  Need to design modules/logic for startup and initialization of each component.  This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.
+
*Use the red Xilinx USB cable box to connect the digital control board to the computer.
−
* Do the parts work on falling or rising edges of the clock?  Most VHDL designs are currently on rising edges, but this can be easily corrected.
+
*The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
−
* The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?
+
*2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected
  
−
== The DAC ==
+
== Xilinx Software ==
  
−
The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/DAC_VHDL.zip here].
+
We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.
  
−
=== Interface (D) ===
+
=== Editing the uParam program ===
 +
*Open Xilinx ISE Project Manager
 +
*In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
 +
*Select uParam within FPGA_ctrl.
 +
*To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
 +
**This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
 +
*The maximum gainmode value can be changed similarly.
 +
*Save the file.
 +
*There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.
  
−
The AD5535 Digital-to-Analog Converter has a three-wire serial interface and an inverted-logic reset signal.  A serial communication transfers one 19-bit word:
+
=== Flashing the program ===
−
 
+
*Now that the program has been changed and saved, open the Xilinx IMPACT program.
−
{| align="center" cellpadding="1" border="1" cellspacing="1"
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*Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
−
|
+
*Open fpga.ipf
−
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
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*There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
−
! colspan="5" text-align:left" | A
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**EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
−
! colspan="14" text-align:left" | DB
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**FPGA on right, volatile and forgets its programming at every powerdown
−
|-
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*Make sure that the digital board has power.
−
| 04 || 03 || 02 || 01 || 00 || 13 || 12 || 11 || 10 || 09 || 08 || 07 || 06 || 05 || 04 || 03 || 02 || 01 || 00
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*Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
−
|}
+
*The following settings should be used when creating the PROM
−
|}
+
**Xilinx flash/prom
−
 
+
**PROM family platform flash
−
* A(4:0) is a 5-bit address to select the target DAC channel.  A4 is the most-significant bit and transfers first.
+
**Device xcf01s [1M]. Add if not already there.
−
* DB(13:0) is a 14-bit voltage code, where <math>V_{out} = 50*V_{RefIn}*\frac{DB(13:0)}{2^{14}}</math>.
+
**Output file name: fpga
−
** DB = 0 yields V<sub>out</sub> = 0.
+
**Save to /TotalTest
−
** DB = 2<sup>14</sup>-1 (full scale) yields V<sub>out</sub> = 49.9969*V<sub>Ref In</sub>.
+
**Format mcs
−
 
+
**Don't add non-config data.
−
The three lines of the interface are ''SYNC'', ''SCLK'', and ''D_in''.  A write to the DAC begins with a falling edge of ''SYNC''.  The next 19 bits (counted off by ''SCLK'') are saved into a shift register  The next transfer begins on another falling edge of ''SYNC'', but transfers do not overlap or interrupt.  A minimum of 200ns is required between exchanges.  ''SCLK'' is ignored except during the 19 shift cycles.  The minimum clock pulse width is 13ns high and 13ns low, yielding a maximum frequency of 77MHz theoretically.  In actual fact the maximum clock frequency is 30MHz and the maximum word frequency is 1.2MHz.  For further details on timing and protocol, see the [http://www.analog.com/en/prod/0%2C2877%2CAD5535%2C00.html AD5535 data sheet] supplied by Analog Devices, in particular "Timing Characteristics" (p.5) and "Functional Description (p.12).
+
**Generate
−
 
+
*Switch back to the boundary scan tab.
−
=== Emulator (D) ===
+
*Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.
−
 
 
−
[[Image:DAC Emulator Block.JPG|thumb|DAC emulator functional block diagram]]
 
−
 
 
−
The functional block diagram for the emulator is shown to the right. The blocks are:
 
−
* '''19-cycle hold'''
 
−
** This block takes the single input pulse (one clock cycle wide) and generates a 19-cycle-wide pulse to tell the shift register how long to read in new data.  It ignores any additional pulses while the 19-cycle pulse is running. It also enforces a gap of one cycle between serial words.
 
−
** inputs
 
−
*** ''Reset'': asynchronous, active-low reset
 
−
*** ''CLK'': clock
 
−
*** ''Begin'': active-low input pulse
 
−
** outputs
 
−
*** ''Go'': 19-cycle pulse
 
−
* '''shift register'''
 
−
** This is a serial-in, parallel-out, 19-bit shift register.  While the enable line is high it clocks in data.  The output is nominally partitioned between address and code, but this is implemented not inside the shift register but by routing the output lines appropriately.
 
−
** inputs
 
−
*** ''Reset'': asynchronous, active-low reset
 
−
*** ''D_in'': data-in serial line
 
−
*** ''En'': enable
 
−
*** ''Clk'': clock
 
−
** outputs
 
−
*** ''Addr'': 5-bit parallel address bus
 
−
*** ''Code'': 14-bit parallel code bus
 
−
* '''follow pulse'''
 
−
** This block monitors the enable line generated by the 19-cycle hold block.  At the end of the pulse it sees a falling edge and sends a single-cycle pulse to notify the terminal registers that the shift register has loaded a complete word and is ready to write.
 
−
** inputs
 
−
*** ''Reset'': asynchronous, active-low reset
 
−
*** ''Clk'': clock
 
−
*** ''D'': 19-cycle input pulse
 
−
** outputs
 
−
*** ''Q'': single-cycle following pulse
 
−
* '''5-to-32 demux'''
 
−
** This block is a 5-to-32 demultiplexer. It uses the address generated by the shift register to direct the read-enable pulse from the follow pulse block to the appropriate terminal register.
 
−
** inputs
 
−
*** ''Select'': 5-bit-wide select bus
 
−
*** ''Data'': data line
 
−
** outputs
 
−
*** ''00:31'': 32 enable lines (on per terminal register)
 
−
* '''terminal register''' (x32)
 
−
** This is a 14-bit, parallel-in, parallel-out register.  There is one terminal register for every channel.
 
−
** inputs
 
−
*** ''Reset'': asynchronous, active-low reset
 
−
*** ''Clk'': clock
 
−
*** ''D'': 14-bit data bus
 
−
*** ''En'': read enable
 
−
** outputs
 
−
*** ''Q'': 14-bit output bus
 
−
 
 
−
=== Controller (D) ===
 
−
 
 
−
[[Image:DAC Controller Block.JPG|thumb|DAC controller functional block diagram]]
 
−
 
 
−
The functional block diagram for the controller is shown to the right.  The blocks are:
 
−
* '''19-cycle hold'''
 
−
** Identical to the component of the same name in the DAC emulator (see above)
 
−
* '''delay'''
 
−
** Delays all signals by one clock cycle
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''D'': signal in
 
−
** outputs
 
−
*** ''Q'': signal out
 
−
* '''shift register'''
 
−
** A 19-bit, parallel-in, serial-out shift register.  It reads in values every clock cycle that Sh/Rd is low and shifts out values every clock cycle that Sh/Rd is high.  The signal is MSB of Addr to LSB of Code.
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''Reset'': asynchronous, active-low reset
 
−
*** ''Addr'': 5-bit address bus
 
−
*** ''Code'': 14-bit code bus
 
−
*** ''Sh/Ld'': positive-logic shift/negative-logic load
 
−
** outputs
 
−
*** ''Q'': serial out line
 
−
 
 
−
== The temperature sensor ==
 
−
 
 
−
The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/Temp_VHDL.zip here].
 
−
 
 
−
=== Interface (T) ===
 
−
 
 
−
The AD7314 temperature sensor uses a four-wire interface related to (and compatible with) the [http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus SPI bus] protocol. The wires are:
 
−
* ''CE'': Chip Enable (input), positive logic enable for ''SCLK''
 
−
* ''SCLK'': Serial Clock (input), clock line supplied by external source
 
−
* ''SDI'': Serial Data In (input), data input line
 
−
* ''SDO'': Serial Data Out (output), data output line
 
−
Note that the input/output notations are for slave devices (such as the temperature sensor) but are reversed for master devices (such as the FPGA).  Proper SPI protocol flips the I/O polarity of ''CE'' and ''SCLK'' and crosses the ''SDI'' and ''SDO'' lines so that ''SDI'' is an input on every device and ''SDO'' is always an output.  To maintain simplicity in wiring conventions we are not using proper SPI protocol, but are calling the slave input/master output line ''SDI'' and the slave output/master input line ''SDO'' so that the ''SDI/O'' notations are proper for slaves.  The maximum clock rate is no higher than 10MHz.  The interface, having separate input and output lines, is full-duplex; in fact the temperature sensor is unable to function in half-duplex mode.  Outputs from the temperature sensor change on rising edges of ''SCLK'', but inputs are latched on falling edges.
 
−
 
 
−
There is only one write operation to the temperature sensor and that is used to direct the temperature sensor to enter power-down mode.  We do not plan to use this mode, so the ''SDI'' input on the temperature sensor will be tied to ground.
 
−
 
 
−
A read operation occurs during a 16-cycle pulse of ''CE''.  The first transmitted bit will be zero, followed by ten bits of temperature data (MSB first).  The remaining five bits are copies of the final data bit.  After ''CE'' goes low ''SDO'' goes into a high-Z state.  Temperature data is given in degrees Celsius.  The format is two's-complement with two decimal places; in essence it is standard two's-complement, then the result must be divide by four after converting to decimal.
 
−
 
 
−
=== Emulator (T) ===
 
−
 
 
−
[[Image:Temp Emulator Block.JPG|thumb|Temperature sensor emulator functional block diagram]]
 
−
 
 
−
The functional block diagram for the emulator is shown to the right.  The blocks are:
 
−
* '''Error Flag'''
 
−
** The error flag goes high if the enable line is high for 1-15 or 17+ cycles.  It resets to low any time the enable line goes back to high.  It is used to notify of a "bad" transmission (not 16 cycles long).
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''En'': enable
 
−
** outputs
 
−
*** ''Err'': error flag
 
−
* '''Shift Reg'''
 
−
** An 11-bit, parallel-in, serial-out shift register that loads when not shifting.
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''Sh/Ld'': active-high shift, active-low load
 
−
*** '' Par(10:0)'': 11-bit parallel input bus
 
−
** outputs
 
−
*** ''Ser'': serial output line
 
−
 
 
−
=== Controller (T) ===
 
−
 
 
−
[[Image:Temp Controller Block.JPG|thumb|Temperature sensor controller functional block diagram]]
 
−
 
 
−
The functional block diagram for the controller is shown to the right.  The blocks are:
 
−
* '''Counter'''
 
−
** Counts a cycle of 17 pulses; holds ''En'' high for 11 pulses, holds ''CE'' high for 16 pulses.
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''Rst'': asynchronous, active-low rest
 
−
*** ''Go'': trigger to begin cycle
 
−
** outputs
 
−
*** ''CE'': serial chip enable
 
−
*** ''En'': internal shift enable
 
−
* '''Delay'''
 
−
** Delays input by one clock cycle.
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''D'': input signal
 
−
** outputs
 
−
*** ''Q'': output signal
 
−
* '''Shift Reg'''
 
−
** A 10-bit, serial-in, parallel-out shift register.
 
−
** inputs
 
−
*** ''Clk'': clock
 
−
*** ''Rst'': asynchronous, active-low rest
 
−
*** ''D'': input signal
 
−
*** ''En'': shift enable
 
−
** outputs
 
−
*** ''Q'': 10-bit output bus
 
−
 
 
−
== The ADC ==
 
−
 
 
−
The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip here].
 
−
=== Interface (A) ===
 
−
 
 
−
The AD7928 ADC has several features that we do not need: the shadow/sequencer and the multiple power modes.  They could be useful for more advanced or efficient functioning of the system, but are not needed.  Thus we will simplify the interface by turning these features off and running the ADC is the most basic mode.
 
−
 
 
−
The ADC has a four-wire interface that is compatible with the SPI bus protocol. The four lines are:
 
−
* ''/CS'': Active-low chip select.  This line is high when the ADC is idle and goes low for 16 cycles during a conversation.  As this is active-low and the only other chip on the bus (the temperature sensor) has an active-high chip select line, it is possible to use a single chip select. That would cause one or the other chip to always be running, which would be more information than we need or than we can send across Ethernet, but it is a possible design decision.
 
−
* ''SCLK'': A serial clock.
 
−
* ''D_out'': Serial data out line, for communications from the ADC to the FPGA.  This line idles in high-Z.
 
−
* ''D_in'': Serial data in line, for communications from the FPGA to the ADC.
 
−
 
 
−
On startup the ADC requires two "dummy" conversation that write all ones to the ADC and read garbage data from the ADC.
 
−
 
 
−
A typical conversation lasts for 16 clock cycles, sends 12 bits to the ADC, and receives 12 bits from the ADC.  The 12-bit control register has the following format:
 
−
 
 
−
{| align="center" cellpadding="1" border="1" cellspacing="1"
 
−
|
 
−
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:left"
 
−
|- style="font-size:smaller; height:10px"
 
−
| style="width:8.33%" |11 || style="width:8.33%" |10 || style="width:8.33%" |09 || style="width:8.33%" |08 || style="width:8.33%" |07 || style="width:8.33%" |06 || style="width:8.33%" |05 || style="width:8.33%" |04 || style="width:8.33%" |03 || style="width:8.33%" |02 || style="width:8.33%" |01 || style="width:8.33%" |00
 
−
|-
 
−
| Write || Seq || DC || Addr<sub>2</sub> || Addr<sub>1</sub> || Addr<sub>0</sub> || Pow<sub>1</sub> || Pow<sub>0</sub> || Shadow || DC || Range || Coding
 
−
|}
 
−
|}
 
−
 
 
−
The sections of the control register are:
 
−
* Write:
 
−
** if 0, do not update the remaining 11 bits of the control register
 
−
** if 1, write new data to the control register
 
−
* Seq: used for a feature we don't need: set to zero
 
−
* DC: don't care
 
−
* Addr(2:0): 3-bit address of channel to report on during next conversation
 
−
* Pow(1:0): used for changing power modes: set to "11"
 
−
* Shadow: used for a feature we don't need: set to zero
 
−
* DC: don't care
 
−
* Range: set to zero
 
−
** if 0, analog input range is 0 to 2*V<sub>Ref</sub>
 
−
** if 1, analog input range is 0 to V<sub>Reg</sub>
 
−
* Coding: set to zero
 
−
** if 0, output is twos-complement
 
−
** if 1, output is binary-coded decimal
 
−
 
 
−
Thus a conversation to read the voltage only (and not update the control register would look like
 
−
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
 
−
| style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X || style="width:15px" | X
 
−
|}
 
−
and a conversation to set up a read on channel A(2:0) would look like
 
−
{| align="center" cellpadding="4" border="0" cellspacing="0" style="text-align:center"
 
−
| style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | A<sub>2</sub> || style="width:15px" | A<sub>1</sub> || style="width:15px" | A<sub>0</sub> || style="width:15px" | 1 || style="width:15px" | 1 || style="width:15px" | 0 || style="width:15px" | X || style="width:15px" | 0 || style="width:15px" | 0
 
−
|}
 
−
where an X is a don't-care state.  Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved.  The don't-care states in bits 9 and 2 we can set to zero.
 
−
 
 
−
The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation.  We are going to use twos-complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.
 
−
 
 
−
The control interface to the FPGA core will be:
 
−
* ''Clk'': input: Clock line
 
−
* ''Rst'': input: Asynchronous, active-low reset line
 
−
* ''Go'': input: Pulse to begin transmission
 
−
* ''Wr'': input: Flag whether or not to write new data to control register
 
−
* ''A(2:0)'': input: Address to write to control register
 
−
* ''C(2:0)'': output: Address of data coming from ADC
 
−
* ''D(11:0)'': output: Data from ADC
 
−
* ''Done'': output: Flag to tell core that new data is ready
 
−
 
 
−
=== Emulator (A) ===
 
−
 
 
−
[[Image:ADC Emulator Block.JPG|thumb|ADC emulator functional block diagram]]
 
−
 
 
−
The functional block diagram for the emulator is shown to the right. The blocks are:
 
−
* '''shift in 16'''
 
−
** This block is a 16-bit shift-in register with asynchronous, active-low reset and shift enable.  Custom outputs select the write bit and the data bits from the input string.  This register is designed to shift all 16 cycles of a transfer, but only make use of the first 12 bits of the input.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''En'': shift enable
 
−
*** ''D'': data in line
 
−
** outputs
 
−
*** ''Q_W'': the write bit from the input string
 
−
*** ''Q_D'': the 11 data bits from the input string
 
−
* '''control reg'''
 
−
** This block is an 11-bit register with asynchronous, active-low reset and a clock enable line.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''En'': read enable
 
−
*** ''D'': data in
 
−
** outputs
 
−
*** ''Q'': data out
 
−
* '''3-to-8 demux'''
 
−
** This block is a 3-to-8 demultiplexer.
 
−
** inputs
 
−
*** ''D'': data to be demuxed
 
−
*** ''S'': 3-bit select
 
−
** outputs
 
−
*** ''Q'': 8-bit output
 
−
* '''error flag'''
 
−
** This block generates a flag to ensure that data in the control register is in the right format (to help verify synchronization).  The format is: d00ddd110000, where a "d" is a don't-care state (0 or 1).
 
−
** inputs
 
−
*** ''D'': data in
 
−
** outputs
 
−
*** ''Err'': active-high error flag
 
−
* '''shift out 15'''
 
−
** This block is a 15-bit shift-out register with asynchronous, active-low reset and a shift/load toggle.  Custom inputs load the address (MSB first) as the first 3 bits and the data as the last 12 bits.  Idle output is a zero.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
 
−
*** ''D'': data in
 
−
*** ''A'': address in
 
−
** outputs
 
−
*** ''Q'': data out
 
−
 
 
−
=== Controller (A) ===
 
−
 
 
−
[[Image:ADC Controller Block.JPG|thumb|ADC controller functional block diagram]]
 
−
 
 
−
The functional block diagram for the controller is shown to the right. The blocks are:
 
−
* '''counter'''
 
−
** This block is a 5-bit counter.  It counts out 17 cycles: from the idle state, a pulse on the Go line begins a count of 16 cycles (during which time CS is low), then on the 17th cycle re-enters the idle state to await another pulse on Go.  The Go line is ignored during a 17-cycle run.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''Go'': pulse to leave idle state
 
−
** outputs
 
−
*** ''CS'': active-low chip select
 
−
* '''delayer'''
 
−
** This block is a single-cycle signal delayer.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''D'': signal to be delayed
 
−
** outputs
 
−
*** ''Q'': delayed signal
 
−
* '''shift out 12'''
 
−
** This block is a 12-bit shift-out register with asynchronous, active-low reset and a shift/load toggle.  Custom inputs load the write bit and address bits, then fill in the remaining bits (W00AAA110000).  The register drags a trailing zero.  The output idles at zero when output is not enabled.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''Sh/Ld'': shift/load toggle; active-high shift enable, active-low load enable
 
−
*** ''D_W'': write bit input
 
−
*** ''D_A'': address bits input
 
−
** outputs
 
−
*** ''Q'': serial output
 
−
* '''shift in 15'''
 
−
** This block is a 15-bit shift-in register with asynchronous, active-low reset and shift enable.  Custom outputs select the address bits and data bits.
 
−
** inputs
 
−
*** ''CLK'': clock
 
−
*** ''Rst'': asynchronous, active-low reset
 
−
*** ''Sh'': shift enable
 
−
*** ''D'': data in
 
−
** outputs
 
−
*** ''A'': address out
 
−
*** ''Q'': data out
 
−
 
 
−
== Ethernet controller ==
 
−
 
 
−
=== Interface (E) ===
 
−
 
 
−
=== Emulator (E) ===
 
−
 
 
−
=== Controller (E) ===
 

Latest revision as of 21:13, 6 January 2014

Current Guide to Flashing the Final Production FPGAs

Physical Setup

  • Use the red Xilinx USB cable box to connect the digital control board to the computer
  • When the Xilinx USB cable box is powered and the control board is off the orange light on the cable box should be orange
  • When the Xilinx USB cable box and the control board are powered the light on the cable box should be green and ready for programming

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Flashing the Program

  1. Open the Project Navigator
    1. On Hermes (as of 1/2014) Start->All Programs->Xilinx Design Tools->ISE Design Tools->64-bit Project Navigator
  2. If the project doesn't load automatically, load the project file Device.xise
    1. Once loaded the top left window should show the hierarchy with xc3s50a-4vq100 as the top device
    2. FPGA_main - behavioral (FPGA_main.vhd) should have three square boxes on the left with the top one being green. This indicates that this is the top-level file
  3. Edit any source files using Vim outside of the Xilinx software
  4. Right click in the bottom left window on Configure Test Device and select "Rerun All"
    1. This will rerun Synthesize-XST, Implement Design, Generate Programming File, and Configure Target Device
  5. Run Generate Target PROM/ACE File
  6. Run Manage Configuration Project (iMPACT)
    1. This will open up the iMPACT program
    2. Be sure to have all other instances of iMPACT closed otherwise it is likely that there will be a communication error between the computer and the FPGA
    3. In the screen that pops up there should be a picture of two squares with Xilinx written in them connected to TDI and TDO
    4. TDI should connect to xcf01s_vo20 with the file device.mcs underneath
    5. The first square should connect to the second with xc3s50a bypass written underneath, which is then connected to TDO
  7. In iMPACT in the top left window click on Create PROM File
    1. This should change the picture on the screen to two devices on the right and a green square on the left with the file fpga_main.bit inside
    2. In the window titled "iMPACT Processes" run Generate File
    3. When this succeeds there should be a message displayed in blue stating that it succeeded. Click on the Boundary Scan tab or on Boundary Scan in the top left window
  8. Click on the left device, which should be labeled as Target and xcf01s_vo20 device.mcs.
  9. Click on Program in the iMPACT Processes window
    1. This should erase any previous programming and flash the new program onto the FPGA

Igor's Guide to Flashing the First Prototype FPGA

Physical Setup

  • Use the red Xilinx USB cable box to connect the digital control board to the computer.
  • The instructions for mapping the colored wires to the digital control board can be found in the "Data Acquisition Station Log + Readout Electronics Project" logbook on pg. 104 in the top left corner.
  • 2->red; 4->green; 6->yellow; 8->purple; 10->white; 13->black; gray is unconnected

Xilinx Software

We use the Xilinx Webpack (free) license. The program and license for tagger-station can be found in /nfs/direct/packages/xilinx.

Editing the uParam program

  • Open Xilinx ISE Project Manager
  • In the top left window select FPGA_ctrl. This should have 2 boxes and a "+" with the top box green. This indicates a top level project.
  • Select uParam within FPGA_ctrl.
  • To change the maximum voltage for VBias, change the binary value for DAC_Qmax.
    • This is a 14-bit number which is found by following the formula commented out in the program. 3.3V has been used for the reference voltage.
  • The maximum gainmode value can be changed similarly.
  • Save the file.
  • There should be orange question marks in the lower left window. Run "generate programming file". Yellow exclamation marks correspond to warnings but not errors.

Flashing the program

  • Now that the program has been changed and saved, open the Xilinx IMPACT program.
  • Open IMPACT and go to the folder c/work/Gluex/Tagger/Electronics/FPGA/TotalTest and check to see if fpga_ctrl.bgn and .bit are up to date
  • Open fpga.ipf
  • There should be 2 diagrams showing the devices on the programming device: TDinput (xcf01s_vo20 fpga.mcs), TDoutput (xc3s50a bypass)
    • EEPROM (on left, chip holds the programming in non-volatile memory and programs FPGA on startup)
    • FPGA on right, volatile and forgets its programming at every powerdown
  • Make sure that the digital board has power.
  • Select Create PROM file in top left window. Xilinx needs to create a new mcs file out of the bit file before the FPGA can be programmed.
  • The following settings should be used when creating the PROM
    • Xilinx flash/prom
    • PROM family platform flash
    • Device xcf01s [1M]. Add if not already there.
    • Output file name: fpga
    • Save to /TotalTest
    • Format mcs
    • Don't add non-config data.
    • Generate
  • Switch back to the boundary scan tab.
  • Select EEPROM then select program in the lower left window. Auto-erase normally occurs but if it doesn't, erase and then program.
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