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Line 81: − == (001) Transmit "I" == − This is a simple state. It loads to the CP2200/1 a packet containing an ASCII "I" in the first byte and padding (any value) in all remaining bytes (minimum size of data is 46 bytes, so there needs to be 45 bytes of padding). After the transmission is complete, the block writes a 010 to the state register. − − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset − * ''State'': 3-bit state value − − internal signals − * ''S_En'': state enable, ''S_En'' <= not ''St(2)'' and ''St(1)'' and not ''St(0)'' − * ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle − − blocks − * '''Transmitter''' − ** Loads an ASCII "I" (0x49, 0100 1001) to the transmitter 46 times (the first value must be "I" and the rest are garbage, so padding with "I" is simplest) to fill in a complete packet (accounts for any register incrementing or other loading control necessary). − ** inputs − *** ''Clk'': clock − *** ''/Rst'': asynchronous, active-low reset − *** ''Go'': pulse to begin sending − *** ''Inc'': ''Done'' signal from transceiver; initiates next sending − ** outputs − *** ''TxRx_A'': ''A_in'' signal to transceiver − *** ''TxRx_D'': ''D_in'' signal to transceiver − *** ''TxRx_R/W'': ''R/W'' signal to transceiver; tied to write (zero) − *** ''TxRx_Go'': ''Go'' signal to transceiver − *** ''Done'': pulses for one cycle; connects to state register as an enable line − *** ''New_St'': new state to load into state register; goes to 010 when ''Done'' is high
Programming the Ethernet controller (view source)
Revision as of 18:57, 16 May 2008
, 18:57, 16 May 2008→Controller
[[FPGA_Reset|Reset Modules]]
[[FPGA_Reset|Reset Modules]]
[[FPGA_Transmitter|Packet Transmitter]]
[[FPGA_Registers|Registers]]
[[FPGA_Registers|Registers]]
== (010) Idle ==
== (010) Idle ==