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Programming the Ethernet controller (view source)
Revision as of 18:41, 28 November 2007
, 18:41, 28 November 2007→Emulator
= Emulator =
= Emulator =
Since the modules described here represent the core of the FPGA, their combined simulation calls for inclusion of all other fringe modules. Essentially the whole FPGA will have to be tested to ensure this scheme for the core is acting properly. The challenge is in the complexity of the stimulus for such simulation: whole packets will need to be sent in and possibly inter-packet Ethernet Controller Chip states tested.
Proper reading of packets can be implemented with a module inside the Transceiver that releases its test buffer byte by byte to simulate the AutoRead mode. A more extensive simulation would be useful which includes the testing of the Intel Muxed bus and which would test packet assembly, sending and Ethernet polling procedures.
= Controller =
= Controller =