Changes

The Xilinx Spartan-3A FPGA we will be using on the SiPM control board can be programmed using any of several modes. This table, adapted from the [http://www.xilinx.com/support/documentation/user_guides/ug332.pdf User Guide], Table 2-1, shows the available programming modes and how to select them by setting the M[2:0] pins on the FPGA.

The Xilinx Spartan-3A FPGA we will be using on the SiPM control board can be programmed using any of several modes. This table, adapted from the [http://www.xilinx.com/support/documentation/user_guides/ug332.pdf User Guide], Table 2-1, shows the available programming modes and how to select them by setting the M[2:0] pins on the FPGA.

For information about the other pins used in the programming process, see [[SiPM digital control board netlist]].

We will be using the [[#Master serial (platform flash) mode | master serial]] programming mode, since it is simplest to set up, requires fewer pins, and we don't need the higher speeds of the other available modes. For our purposes, reducing the number of pins on the EEPROM and the number of leads on the board is more important than reducing the start-up time of the FPGA.

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|'''Programming Mode'''

|'''Programming Mode'''

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|Master serial (platform flash) mode

| bgcolor="#99ff99" | Master serial (platform flash) mode

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=== SPI mode ===

 

=== Master serial (Platform Flash) mode ===

When programmed in SPI mode, the variant select pin

Operating in master serial mode, the FPGA generates its own clock signal during the programming process. This clock signal is output through the FPGA's CCLK pin (see [[SiPM digital control board netlist#Configuration pins | FPGA Configuration Pins]]). When used with a compatible [http://www.xilinx.com/products/silicon_solutions/proms/pfp/spartan.htm Xilinx EEPROM], the FPGA can read data from the EEPROM by driving the EEPROM's CE and OE pins high, and waiting for CF to rise. New data is available on the D0 pin a short while after each rising clock edge.