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Digital control board debugging notes (view source)
Revision as of 15:38, 30 September 2010
, 15:38, 30 September 2010no edit summary
This page contains a list of all currently known problems with the digital control board.
This page contains a list of all currently known problems with the digital control board.
== Resistor on DAC temperature measurement diode too high ==
=== Description ===
When the readout is programmed using the DAC manual's coefficients and offset, the temperature value ends up tens of degrees off.
=== Cause/Solution ===
The board was designed with R1=270kΩ to sink the current from the DAC's internal temperature-measuring diode to ground. The manual specifies the expected diode drop at 25degC will be 0.65V at a current of 100uA. Given the sensitivity of this device (with a coefficient of 2.2mV/degC) it is seems best to match their measurement conditions and adjust the resistor so that 0.65V drop from the biasing 5V results in 100uA through the resistor. So, ''R1 should be set to 43.5kΩ''.
Three parallel resistors have been soldered into place on the prototype board providing a nominal R1 of 43.6kΩ. The readout values are now reasonable.
== No Power on +1.2V Power Island ==
== No Power on +1.2V Power Island ==
* June 22, 2009: One board has been modified to correct this problem.
* June 22, 2009: One board has been modified to correct this problem.
== SPI Bus Miswired ==
== SPI Bus Miswired ==
=== Cause ===
=== Cause ===
FPGA pin 5 (labelled SPI) is connected to DIN on the ADC, and DOUT of the temperature sensor. FPGA pin 96 (labelled AD7928/DOUT) is connected to DOUT on the ADC. SPI designates that all slave device DOUT traces be connected together. Chip select and HiZ logic are used to prevent devices from fighting over the signal line.
FPGA pin 5 (labelled SPI) is connected to DIN on the ADC, and DOUT of the temperature sensor. FPGA pin 97 (labelled AD7928/DOUT) is connected to DOUT on the ADC. SPI designates that all slave device DOUT traces be connected together. Chip select and HiZ logic are used to prevent devices from fighting over the signal line.
=== Solution ===
=== Solution ===
This problem was due to errors int he original schematics. The schematics have '''not yet been updated''' to reflect the solution.
This problem was due to errors int he original schematics. The schematics have '''not yet been updated''' to reflect the solution.
This modification has been implemented.
== Incorrect Oscillator ==
=== Description ===
The oscillator used was a standard crystal oscillator, however the FPGA requires an oscillator with a CMOS square wave input.
=== Solution ===
The crystal oscillator was replaced with a FOX FXO-HC53 HCMOS oscillator running at 20 Mhz. The output from the oscillator was connected to pin 27 on the FPGA. The load of having both the oscillator and the Ethernet controller connected to the output of the oscillator was to large. The clock input for the Ethernet controller Pin 28 was connected to pin 37 of the FPGA.
Schematic:[[Image:osc.png]]
=== Other Details and Current Status ===
The schematics have '''not yet been updated''' to reflect the solution.
This modification has been implemented.
== Wrong polarity of Zener Diode on -5V ==
=== Description ===
Zener diode D2 is reversed in the layout. It is correct in the schematics.
=== Solution ===
The diode was rotated on all the prototyping boards. This indication has '''not yet been entered into the layout'''.
=== Other Details and Current Status ===
This problem may be related to the overload on the -5V circuitry for of the DAC.
== Mismatched JTAG programming header ==
=== Description ===
The connector of the "Xilinx Platform USB II" kit seems to be a reduced size compared to the standard 0.1" spaced pin header with which the board is equipped.
=== Solution ===
For the testing stage, the flying lead connector is sufficient to bypass this problem. The layout must be corrected to the matching header (type?). Change entered already?
== Ethernet jack pinout mismatch ==
The wrong Ethernet jack was attached to the PCB, leading to a pinout mismatch. The part ordered was the Pulse J001'''1'''D21. The correct part is J001'''2'''D21. The correct part was ordered and soldered onto the prototype boards, but this change must be made in the Altium parts list.
= Suggested/Preferred Changes =
* <code>R12</code>, the pull-up resistor for the reset pins (header 2) is unnecessary, as the FPGA pin can be programmed to pull up.