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Amplifier board debugging notes (view source)
Revision as of 01:48, 29 September 2010
, 01:48, 29 September 2010no edit summary
* the ICs were rotated such that 2 pins (Vref and Gnd) are bonded to their nets. The loose Vz pin was connected via wire to its proper proper net.
* the ICs were rotated such that 2 pins (Vref and Gnd) are bonded to their nets. The loose Vz pin was connected via wire to its proper proper net.
* '''modifications of the PCB layout is pending'''
* '''modifications of the PCB layout is pending'''
== Change of reference for summing circuit CD level ==
The new PNP input stage of the summing circuit, in order to be placed far from cutoff and saturation, is very sensitive to its emitter current, which, with RE=154Ω requires transistor base control on the order of 10mV. Basically, we need the set the base for the desired emitter voltage and accounting for the diode drop ''referencing Vcc, not ground, as it was with NPN''. The shunt voltage regulators used so far can be employed for this, but the ~0.9V offset from Vcc cannot be done with most regulators as they use a double diode drop - 1.24V as internal reference and allow settings above this value. A reference NCP100 SNT 1G (On semiconductors) has been chosen because of it's lower possible settings, making reference to just one diode drop: 0.698V
The adjacent diagram shows the necessary circuit.