Aaron Carta Undergraduate Research Progress, Fall 2013

This page is a summary of the work I did under the supervision of Dr. Richard Jones, in the fall semester of 2013 at the University of Connecticut.

DAQ Station

Towards the end of the summer, Jefferson Lab National Accelerator Facility loaned our research group a DAQ (Data Acquisition) workstation. It is essentially a "crate" computer, consisting of several specialized electronics boards. In order to be able to make sense of the DAQ station and how to use it for fiber testing, I had to learn about each of the components.

The CPU, named halldtrg5 and networked with Dr. Jones's cluster at the address halldtrg5.phys.uconn.edu, is in slot 1 (where the slots are labelled in increasing order from left to right).

Trigger Interface

A PCI Trigger Interface Card resides in slot 2. The PCI interface is a PLX 9056, running 32-bit at 66MHz, and in a PCI interface. The PCI is connected an FPGA (Field Programmable Gate Array), and this configuration supports only 32-bit read and write transactions (burst or non-burst).

The board mounted in the halldtrg5 crate consists of the PCI interface, the FPGA, the Trigger Supervisor interface, and the Local Trigger Interface.

The Local Trigger interface allows an external trigger to be connected to the Trigger Interface, via the front panel. In my initial tests, I connected a function generator to this external trigger interface.

The Trigger Supervisor Interface, on the front panel of the Trigger Interface below the Local Trigger, allows connection to readout controllers (ROC).

In either case, information from either of the front panel trigger interfaces is passed to the FPGA. This communicates with the PCI interface on the board, and thus with the CPU.

F-ADC

SDC

LE Discriminator

TDC