Difference between revisions of "Aaron Carta Undergraduate Research Progress, Fall 2013"
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==DAQ Station== | ==DAQ Station== | ||
| − | Towards the end of the summer, Jefferson Lab National Accelerator Facility loaned our research group a DAQ (Data Acquisition) workstation. It is essentially a "crate" computer, consisting of several specialized electronics boards. In order to be able to make sense of the DAQ station and how to use it for fiber testing, I had to learn about each of the components. | + | Towards the end of the summer, Jefferson Lab National Accelerator Facility loaned our research group a DAQ (Data Acquisition) VME workstation. It is essentially a "crate" computer, consisting of several specialized electronics boards. In order to be able to make sense of the DAQ station and how to use it for fiber testing, I had to learn about each of the components. |
The CPU, named halldtrg5 and networked with Dr. Jones's cluster at the address halldtrg5.phys.uconn.edu, is in slot 1 (where the slots are labelled in increasing order from left to right). | The CPU, named halldtrg5 and networked with Dr. Jones's cluster at the address halldtrg5.phys.uconn.edu, is in slot 1 (where the slots are labelled in increasing order from left to right). | ||
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In either case, information from either of the front panel trigger interfaces is passed to the FPGA. This communicates with the PCI interface on the board, and thus with the CPU. | In either case, information from either of the front panel trigger interfaces is passed to the FPGA. This communicates with the PCI interface on the board, and thus with the CPU. | ||
| − | ''' | + | '''fADC''' |
| + | |||
| + | Crucial to the operation of the DAQ crate is the lash Analog-to-Digital Converter (fADC), mounted in slot 5. The board in the halldtrg5 crate is an fADC-250, manufactured by Jefferson Lab. This is a 16 channel, pipelined fADC designed for use with VME crates. It can run in 8, 10, and 12-bit modes, at 250 MSPS. | ||
| + | |||
| + | Via this board, cosmic tests and other procedures will be conducted on the optical fibers that are to be used in the construction of the full-scale tagger microscope. Electronics will be connected to the 16 front-panel connections, and this will be read to the Trigger Interface/CPU. | ||
| − | |||
'''LE Discriminator''' | '''LE Discriminator''' | ||
| + | |||
| + | Leading Edge discriminators look only at the leading edge of a signal. When the signal reaches a certain threshold, the discriminator emits a logic pulse, which is read by the Trigger Interface. This relatively simple discriminator device, mounted in slot 14, is not currently used in our DAQ setup, though it is connected to the Trigger Interface should its use become necessary. | ||
'''TDC''' | '''TDC''' | ||
| + | Mounted in slot 16 is the time-to-digital converter (TDC), in this case an F1TDC. This TDC has high resolution (up to 60 pS LSB), and is capable of storing up to one million hits. Its front panel consists of a differential ECL input, and either 64 or 32 other input channels, depending on whether the TDC is running in 120 pS LSB of 60 pS LSB mode, respectively. | ||
Revision as of 18:47, 23 December 2013
This page is a summary of the work I did under the supervision of Dr. Richard Jones, in the fall semester of 2013 at the University of Connecticut.
DAQ Station
Towards the end of the summer, Jefferson Lab National Accelerator Facility loaned our research group a DAQ (Data Acquisition) VME workstation. It is essentially a "crate" computer, consisting of several specialized electronics boards. In order to be able to make sense of the DAQ station and how to use it for fiber testing, I had to learn about each of the components.
The CPU, named halldtrg5 and networked with Dr. Jones's cluster at the address halldtrg5.phys.uconn.edu, is in slot 1 (where the slots are labelled in increasing order from left to right).
Trigger Interface
A PCI Trigger Interface Card resides in slot 2. The PCI interface is a PLX 9056, running 32-bit at 66MHz, and in a PCI interface. The PCI is connected an FPGA (Field Programmable Gate Array), and this configuration supports only 32-bit read and write transactions (burst or non-burst).
The board mounted in the halldtrg5 crate consists of the PCI interface, the FPGA, the Trigger Supervisor interface, and the Local Trigger Interface.
The Local Trigger interface allows an external trigger to be connected to the Trigger Interface, via the front panel. In my initial tests, I connected a function generator to this external trigger interface.
The Trigger Supervisor Interface, on the front panel of the Trigger Interface below the Local Trigger, allows connection to readout controllers (ROC).
In either case, information from either of the front panel trigger interfaces is passed to the FPGA. This communicates with the PCI interface on the board, and thus with the CPU.
fADC
Crucial to the operation of the DAQ crate is the lash Analog-to-Digital Converter (fADC), mounted in slot 5. The board in the halldtrg5 crate is an fADC-250, manufactured by Jefferson Lab. This is a 16 channel, pipelined fADC designed for use with VME crates. It can run in 8, 10, and 12-bit modes, at 250 MSPS.
Via this board, cosmic tests and other procedures will be conducted on the optical fibers that are to be used in the construction of the full-scale tagger microscope. Electronics will be connected to the 16 front-panel connections, and this will be read to the Trigger Interface/CPU.
LE Discriminator
Leading Edge discriminators look only at the leading edge of a signal. When the signal reaches a certain threshold, the discriminator emits a logic pulse, which is read by the Trigger Interface. This relatively simple discriminator device, mounted in slot 14, is not currently used in our DAQ setup, though it is connected to the Trigger Interface should its use become necessary.
TDC Mounted in slot 16 is the time-to-digital converter (TDC), in this case an F1TDC. This TDC has high resolution (up to 60 pS LSB), and is capable of storing up to one million hits. Its front panel consists of a differential ECL input, and either 64 or 32 other input channels, depending on whether the TDC is running in 120 pS LSB of 60 pS LSB mode, respectively.