Digital control board documentation
This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.
Power Requirements
Required Voltages
All components on the digital board except the DAC can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage. Digital and analog grounds must be connected as well before any testing takes place.
Power Pins
Power shall be connected to the board as follows:
| Voltage | Eurocard Pin |
| DGND | A6 |
| AGND | A5 |
| +5V | A4 |
| -5V | A3 |
| High voltage (DAC max out +10, not to exceed +210V) |
A2 |
Power Supply Sequencing
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:
- Ensure AGND/DGND are connected/grounded
- +5V
- -5V
- High voltage
FPGA
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.
Power Details
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.
Logic Standard
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a 3.3V CMOS logic standard.
Pinout Table
| Pin # | Net Name | Description |
| P1 | FPGA/TMS | JTAG |
| P2 | FPGA/TDI | JTAG |
| P3 | AD7928/CS | SPI chip select for ADC |
| P4 | SPI | Erroneously wired SPI bus trace Connects to SDO on temp. sensor and DIN on ADC |
| P5 | CLK_5MHZ | 5 MHz clock output for SPI bus (ADC and temp. sensor) |
| P6 | No connection | |
| P7 | No connection | |
| P8 | DGND | |
| P9 | No connection | |
| P10 | No connection | |
| P11 | +3.3V | |
| P12 | No connection | |
| P13 | No connection | |
| P14 | DGND | |
| P15 | No connection | |
| P16 | No connection | |
| P17 | +1.2V | |
| P18 | DGND | |
| P19 | No connection | |
| P20 | No connection | |
| P21 | No connection | |
| P22 | +3.3V | |
| P23 | DGND | |
| P24 | DGND | |
| P25 | DGND | |
| P26 | +3.3V | |
| P27 | FPGA/CLK_IN | 20 MHz clock input from crystal oscillator |
| P28 | No connection | |
| P29 | No connection | |
| P30 | No connection | |
| P31 | No connection | |
| P32 | No connection | |
| P33 | No connection | |
| P34 | No connection | |
| P35 | CP2201/INT | Ethernet controller interrupt |
| P36 | MASTER_RESET | Connects to RESET jumper in upper left of board (active-low, externally pulled up) |
| P37 | No connection | |
| P38 | +1.2V | |
| P39 | No connection | |
| P40 | CP2201/CS | Chip select for ethernet controller |
| P41 | CP2201/WR | Write enable for ethernet controller |
| P42 | DGND | |
| P43 | CP2201/RD | Read enable for ethernet controller |
| P44 | CP2201/ALE | Address line enable for ethernet controller |
| P45 | +3.3V | |
| P46 | CP2201/RESET | Reset pin for ethernet controller |
| P47 | DGND | |
| P48 | FPGA/INIT_B | Used during FPGA configuration - see Xilinx documentation |
| P49 | CP2201/AD0 | Ethernet controller address/data bus, bit 0 |
| P50 | CP2201/AD1 | Ethernet controller address/data bus, bit 1 |
| P51 | FPGA/DIN | Serial data input from EEPROM for configuration |
| P52 | CP2201/AD2 | Ethernet controller address/data bus, bit 2 |
| P53 | FPGA/CCLK | Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation |
| P54 | FPGA/DONE | Gives configuration status - see Xilinx documentation |
| P55 | +3.3V | |
| P56 | CP2201/AD3 | Ethernet controller address/data bus, bit 3 |
| P57 | CP2201/AD4 | Ethernet controller address/data bus, bit 4 |
| P58 | DGND | |
| P59 | CP2201/AD5 | Ethernet controller address/data bus, bit 5 |
| P60 | CP2201/AD6 | Ethernet controller address/date bus, bit 6 |
| P61 | CP2201/AD7 | Ethernet controller address/date bus, bit 7 |
| P62 | No connection | |
| P63 | DGND | |
| P64 | No connection | |
| P65 | No connection | |
| P66 | +1.2V | |
| P67 | +3.3V | |
| P68 | +3.3V | |
| P69 | DGND | |
| P70 | ID3 | Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high |
| P71 | ID2 | Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high |
| P72 | ID1 | Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high |
| P73 | ID0 | Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high |
| P74 | DGND | |
| P75 | FPGA/TDO | JTAG |
| P76 | FPGA/TCK | JTAG |
| P77 | ID4 | Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high |
| P78 | No connection | |
| P79 | +3.3V | |
| P80 | DGND | |
| P81 | +1.2V | |
| P82 | No connection | |
| P83 | CLK_5MHZ_2 | 5 MHz clock output for DAC |
| P84 | No connection | |
| P85 | AD5535/DIN | DAC serial data input (FPGA out -> DAC in) |
| P86 | No connection | |
| P87 | DGND | |
| P89 | No connection | |
| P90 | No connection | |
| P91 | DGND | |
| P92 | +3.3V | |
| P93 | AD7314/CE | Chip enable for temperature sensor |
| P94 | No connection | |
| P95 | DGND | |
| P96 | +3.3V | |
| P97 | AD7928/DOUT | Erroneously wired ADC SPI bus connection Connects to DOUT on ADC |
| P98 | AD5535/RESET | Reset pin for DAC |
| P99 | DGND | |
| P100 | FPGA/PROG_B | Used during FPGA configuration - see Xilinx documentation |
EEPROM
To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.
Power Details
The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.
Flashing/Burning/Writing
Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.
FPGA Configuration
The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.
Pinout Table
| Pin # | Net Name | Description |
| 1 | FPGA/DIN | Serial data line Carries data from the EEPROM to the FPGA |
| 2 | No connection | |
| 3 | FPGA/CCLK | Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration |
| 4 | EEPROM/TDI | This is the EEPROM's TDI This is the entry point for the onboard JTAG chain |
| 5 | FPGA/TMS | JTAG TMS Connects to both FPGA and EEPROM |
| 6 | FPGA/TCK | JTAG TCK Connects to both FPGA and EEPROM |
| 7 | FPGA/PROG_B | Used during configuration See Xilinx documentation |
| 8 | FPGA/INIT_B | Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation |
| 9 | No connection | |
| 10 | FPGA/DONE | Indicates completion of FPGA configuration High when complete |
| 11 | DGND | |
| 12-16 | No connection | |
| 17 | FPGA/TDI | This is the EEPROM's TDO/FPGA's TDI |
| 18-20 | +3.3V |