FPGA Querier

See also Programming the Ethernet Controller for a survey of modules and a general discussion of FPGA design approach.

(100) Query Sensor Chips

The Querier performs a poll of the sensor chips: Temperature Sensor and the 8-channel ADC. The returned values from these combined nine polls are stored in the Temperature and ADC registers.

This block will have at least two functional blocks: one to poll the temperature sensor and one to poll the ADC. Its job is to update all status values from the status chips in preparation for transmission. Additionally, it converts all values to 16-bit two's-complement before storing locally. Once all status values have been updated it transitions to state 101.

Currently we assume that data values will be stored in the FPGA. If data values will be stored on CP2200/1 Flash memory or other storage device, the interfaces and blocks will have to be adjusted appropriately.

inputs

• Clk: clock
• /Rst: asynchronous, active-low reset
• State: 3-bit state value

internal signals

• S_En: state enable, S_En <= not (St(2) or St(1) or St(0))
• Go: when S_En goes high Go pulses for one cycle

blocks

• ADC Poll
  • Updates values stored in the FPGA from the ADC. Obtains data from ADC, converts to 16-bit two's-complement, and stores.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: go pulse to begin
  • outputs
    • - All ADC control lines -
    • A_Done: goes high when reset/initialization process is complete, falls on Go pulse
    • En: enable line for writing to the internal registers
    • Sel: 3-bit select bus to specify which ADC channel data is available
    • Data: 16-bit data bus to carry data to FPGA internal registers
• Temp Poll
  • Updates value stored in the FPGA from the temperature sensor. Obtains data from temperature sensor, converts to 16-bit two's-complement, and stores.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: go pulse to begin
  • outputs
    • - All temperature sensor control lines -
    • En: enable line for writing to the internal register
    • Data: 16-bit data bus to carry data to FPGA internal registers
• Coordinator
  • Coordinates the completion of each polling cycle and notifies other blocks that the polling process is complete.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • A_Done: high when ADC is done polling
  • outputs
    • Done: when A_Done goes high, Done pulses for one cycle; connects to state register as an enable

    Note that the temperature sensor does not signal completion. That is because the temperature sensor need only update one value, while the ADC must update eight values. Thus it is known ahead of time that the temperature sensor will already be done by the time the ADC is done.

    • New_St: new state to be written to the state register; goes to 101 while Done is high