VHDL tutorial

VHDL Tutorial A brief guide to VHDL design with a design example; the introduction and core of the tutorial. < prev next >

FPGA programming using a hardware description language is not a commonly taught skill in physics programs, but is a necessary skill for designing the electronics required for this project. This tutorial aims to layout the design process and teach the basics of hardware description language; in particular VHDL. The main competitor to VHDL is Verilog; tutorials and information regarding Verilog can be found through Google web searching.

Design example

To illustrate the discussions in this tutorial, a design example is discussed along the way. The design example is the emulator for the AD5535 DAC. As each step of the design process is discussed, the DAC emulator will be used for illustration.

The tutorial

Due to the length of the tutorial, it had to be broken into several pages. Here are the links to the various sections of the tutorial. The first three sections discuss VHDL itself. The final section is about using the development environment provided by Xilinx; you can read this section first or last as you see fit.

• VHDL: Where to start - Section one of the tutorial, focusing on preparing your design for coding.
• VHDL: Enter the code monkey - Section two of the tutorial, focusing on outlining the framework of your code.

See also: code monkey

• VHDL: The real code - Section three of the tutorial, focusing on coding the body of your design.
• VHDL: Xilinx ISE - Section four of the tutorial, focusing on using the development environment.

Extras

Here is some extra information regarding VHDL to be used as reference material.

VHDL Resolution Table

VHDL STD_LOGIC and STD_LOGIC_VECTOR both operate on 9-value logic defined by IEEE. The nine states are:

• U: uninitialized
• X: forcing unknown
• 0: forcing 0
• 1: forcing 1
• Z: high impedance
• W: weak unknown
• L: weak 0
• H: weak 1
• –: don't care

If you have two or more drivers for the same line, then VHDL must somehow resolve the conflict. The resolution table is given below.

VHDL Resolution Table

	U	X	0	1	Z	W	L	H	–
U	U	U	U	U	U	U	U	U	U
X	U	X	X	X	X	X	X	X	X
0	U	X	0	X	0	0	0	0	X
1	U	X	X	1	1	1	1	1	X
Z	U	X	0	1	Z	W	L	H	X
W	U	X	0	1	W	W	W	W	X
L	U	X	0	1	L	W	L	W	X
H	U	X	0	1	H	W	W	H	X
–	U	X	X	X	X	X	X	X	X

Links

In case you can't follow the near-incoherent ramblings that constitute my tutorial, here are links to some others. And always remember: Google is a programmer's best friend.

• http://esd.cs.ucr.edu/labs/tutorial/
• http://www.vhdl-online.de/tutorial/