Line 45:
Line 45:
−
[[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines
+
[[FPGA_Registers#MAC_Address_Registers|MAC Address Register]] Control Lines
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_En'': [out] register enable (write) signal
* ''MACregs_A'': [out] byte address (4-bit)
* ''MACregs_A'': [out] byte address (4-bit)
Line 60:
Line 60:
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
−
== Programming Details of Rest_soft ==
== Programming Details of Rest_soft ==