Programming the FPGA

The FPGA is the hub of the digital control board and all other chips are connected to and controlled by it. This article discusses the programming of the FPGA. All code is written in VHDL. For the purposes of testing, each chip has not only a controller written for it, but an emulator as well.

Open questions

Programming of the FPGA is an ongoing project, so more questions may be added as the project develops.

What is the clock speed of the FPGA? Timing constraints must be taken into account to link the multiple blocks.
Current designs (11 July, 2007) account for normal activity. Need to design modules/logic for startup and initialization of each component. This should not be only on startup; we should be able to send a reset packet over Ethernet to trigger a reinitialization of each chip.
Do the parts work on falling or rising edges of the clock? Most VHDL designs are currently on rising edges, but this can be easily corrected.
The temperature sensor and the ADC share the same SPI-like bus lines; can they be combined into a single VHDL design?

Component code

Reset and Initialization

On start-up the FPGA must reset and initialize each component; especially the Ethernet controller. Functionality will also be supplied to reset the system on a command from the PC.

The DAC

The AD5535 DAC has an active-low reset pin. Pulling that pin low will reset the DAC, zeroing all channels.

The temperature sensor

The AD7314 temperature sensor does not have a reset function. It self-initializes on powering up.

The ADC

The AD7928 ADC does not have a reset pin, but does require that certain internal registers be reset upon powering up. The reset procedure is to hold the D_in line high while performing two dummy conversions. During both dummy conversions, as well as the third conversation (during which good data can be loaded), invalid data will be returned to the FPGA. It may be worth considering adding a third conversion to the startup procedure that sets the control register to a certain known setting according to our specifications; perhaps setting the next conversion to return channel zero simply as a known point of operation.

The Ethernet controller

The CP2200/1 has a complex reset process, which is laid out in detail in the data sheet (see section 6.2 "Reset Initialization"). The main points of the process will be covered here.

The first step is to wait for the reset pin to rise. No flag will be raised upon the completion of this step other than the reset pin (which is an input to the CP2200/1) being high.
The second step is to wait for Oscillator Initialization to complete. Completion of this will be signaled by an interrupt request signal.
The third step is to wait for Self Initialization to complete. Completion of this will also be signaled by an interrupt request signal.
At this point all interrupts will be enabled. Any interrupts which the FPGA will not handle should be disabled now.
The physical layer must be initialized, which is itself a multi-step process.
- See section 15.7 "Initializing the Physical Layer"
- If auto-negotiation is to be used see section 15.2 "Auto-Negotiation Synchronization."
Enable the Link, Act, or Activity/Link LED(s).
The MAC must now be initialized, another multi-step subprocess.
- See section 14.1 "Initializing the MAC."
The receive filter must now be configured.
- See section 12.4 "Initializing the Receive Buffer, Filter and Hash Table."
The CP2200/1 is now ready for regular operation.

This process should be used sparingly because (1) it is a long, complex process that renders the board unusable for a short time and (2) while the CP2200/1 is initializing the board and the PC are unable to communicate.