FPGA Transmitter

(101) Transmit "S"

This block compiles the status values into a single packet by loading them into the CP2200/1 in a defined order and format, including padding/converting any values that need it. Once the packet has been sent, the block transitions to state 010.

inputs

• Clk: clock
• /Rst: asynchronous, active-low reset
• State: 3-bit state value

internal signals

• S_En: state enable, S_En <= not (St(2) or St(1) or St(0))
• Go: when S_En goes high Go pulses for one cycle

blocks

• Temp Loader
  • This block reads the temperature value from the internal registers and loads it to the transmit buffer.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: pulse to begin; feeds from Go internal signal of block 101
    • D_in: 16-bit data bus from internal registers
    • TxRx_Done: Done signal from transceiver
  • ouputs
    • TxRx_Go: Go signal on transceiver
    • TxRx_R/W: R/W signal on transceiver
    • TxRx_A: A_in bus on transceiver
    • TxRx_D: D_in bus on transceiver
    • Done: pulse to signal completion
• ADC Loader
  • This block reads the ADC values from the internal registers and loads them to the transmit buffer in order: channel zero to channel seven.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: pulse to begin; feeds from Done signal of Temp Loader
    • D_in: 16-bit data bus from internal registers
    • TxRx_Done: Done signal from transceiver
  • ouputs
    • Sel: 3-bit select bus for internal registers
    • TxRx_Go: Go signal on transceiver
    • TxRx_R/W: R/W signal on transceiver
    • TxRx_A: A_in bus on transceiver
    • TxRx_D: D_in bus on transceiver
    • Done: pulse to signal completion
• Padder
  • This block pads the packet to the minimum 46 bytes. Only 19 bytes have been loaded by this point (1 byte "S", 2 byte temperature, 8 x 2 byte ADC), so 27 bytes of padding (zero) must be loaded.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: pulse to begin; feeds from Done signal of ADC Loader
    • TxRx_Done: Done signal from transceiver
  • outputs
    • TxRx_Go: Go signal on transceiver
    • TxRx_R/W: R/W signal on transceiver
    • TxRx_A: A_in bus on transceiver
    • TxRx_D: D_in bus on transceiver
    • Done: pulse to signal completion
• Sender
  • This block tells the CP2200/1 to send the completed packet.
  • inputs
    • Clk: clock
    • /Rst: asynchronous, active-low reset
    • Go: pulse to begin; feeds from Done signal of Padder
    • TxRx_Done: Done signal from transceiver
  • outputs
    • TxRx_Go: Go signal on transceiver
    • TxRx_R/W: R/W signal on transceiver
    • TxRx_A: A_in bus on transceiver
    • TxRx_D: D_in bus on transceiver
    • Done: pulse to signal completion