VHDL: Xilinx ISE
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Now that we've discussed VHDL itself, it's time to learn the development environment. If you don't already have it installed, you will want to install the Xilinx ISE WebPACK. The ISE Foundation is a professional tool that will cost you an arm and a leg. The ISE WebPACK is a free version of the software that does most of what you need (unless you have large, complex designs or are working with the newest and best Xilinx FPGAs). If you know ahead of time which series of FPGAs you plan to use, you can save time and disk space by only installing the files for that FPGA series. Once you've got that installed, fire it up.
Creating a new project
If you already started a project, just select File > Open Project and find your project file. Otherwise, we'll start a new one from scratch.
Go to File > New Project to start the New Project Wizard. Give your project a name. Something not too long that will help you find the files later. Then give the program a location to put the project; ISE will create a subfolder in that directory with the name of your project. And finally, your top-level source type is HDL (Hardware Description Language).
The next dialog box asks a whole lot of questions. But worry not; we'll keep it fairly simple. Choose your device family; for our project that will be the Spartan-3A (on the pull-down menu you'll find "Spartan3A and Spartan3AN"). The device is unknown for our project. We plan to design the VHDL first, then find out how large of an FPGA we need to hold our design. So just go ahead and pick the smallest Spartan-3A: XC3S50A. If need be we'll adjust the project later to use a larger FPGA. If you know the package, go ahead and select that. However, once again, we'll probably figure that out later, so I just left the default. Skimming down past several options you can leave alone (unless you know you're using something other than the defaults), make sure your simulator is set to "ISE Simulator (VHDL/Verilog) and your preferred language is VHDL. Then go ahead and hit next.
If you want to create a brand-new file right up front, go ahead. However, I will explain creating new files a bit later, so you can just skip this step and add the files later. Click next. If you have existing source files from somewhere else that you want to include, this is the place for you. Chances are you're starting from scratch, so you can just click next. Then you get a summary box to make sure you got everything right. If so, click Finish.
Creating a new VHDL file
So you've got a project. Now you need some files in your project. Go to Project > New Source. Select "VHDL Module", give your file a name (don't bother with the .vhd; ISE will add that for you) and a parent directory. Click next. Here's where you start to love ISE, as it will do some work for you. If you read the previous pages of the tutorial, you read about entities, architectures, and ports. ISE now gives you a GUI to define these; give your entity and architecture a name. If you know what your ports will be, go ahead and define them: a name, in/out/inout, line/bus, indices if you're using a bus. If you don't know what your ports will be (or want to change them later), you can just edit the code manually with no problems. Click next. You get a screen to verify all the details you just set up and if you're all set, click finish. The new file will be added to the Sources box to the top left and will open up in the main window. The file will have all sorts of predefined code for you; the library/use statements, some standard comments to describe the file, and the framework for your code.
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If you already had a file created and you just wanted to open it, take a look at the Sources box to the top left. Make sure the pull-down menu above it is set for "Synthesis/Implementation" and the "Sources" tab is selected below it. Double-click the file you want. Depending on your code, ISE will sort your files into hierarchies at times, so you may need to click the little plus signs to find the desired file. Take a look at the image to the left to see what the Sources box looks like.