Difference between revisions of "SiPM digital control board supporting components"
(→XCF01S EEPROM: added connection diagram for EEPROM) |
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=== XCF01S EEPROM === | === XCF01S EEPROM === | ||
| + | [[Image:SiPM FPGA and EEPROM Connections.gif|thumb|Connection diagram for XCF01S and Spartan-3A FPGA taken from<br>[http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf XCF01S specifications sheet].]] | ||
The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. | The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA. | ||
| − | TODO: Insert information about logic levels. | + | TODO: Insert information about logic levels. |
Revision as of 14:56, 25 June 2008
Overview
While the FPGA, Ethernet controller, DAC, ADC and Temperature sensor are considered the main components of the SiPM digital control board, there are also many other supporting components that will be on the board. This page discusses many of the other minor components on the SiPM digital control board.
FPGA Supporting Components
XCF01S EEPROM
The Xilinx XCF01S EEPROM is responsible for configuring the FPGA when the system is turned on or reset. We selected the XCF01S because it is recommended by Xilinx as the best solution for programming the Spartan-3A FPGA used on the control board. The XCF01S is ideal because it has sufficient memory to hold the entire FPGA program, and also minimizes the number of FPGA-to-EEPROM leads necessary for programming the FPGA.
TODO: Insert information about logic levels.