Difference between revisions of "FPGA Registers"
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Senderovich (talk | contribs) m |
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| Line 5: | Line 5: | ||
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
| − | * '' | + | * ''Rst'': asynchronous, reset to zero the register (puts system into reset state) |
* ''En'': write enable | * ''En'': write enable | ||
* ''D'': three-bit data-in bus | * ''D'': three-bit data-in bus | ||
| Line 15: | Line 15: | ||
=== Packet Type Register === | === Packet Type Register === | ||
An 8-bit register to store the 2nd byte of an accepted packet. | An 8-bit register to store the 2nd byte of an accepted packet. | ||
| + | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
| − | * '' | + | * ''Rst'': asynchronous reset to zero the register |
* ''En'': write enable | * ''En'': write enable | ||
* ''D'': 8-bit data-in bus | * ''D'': 8-bit data-in bus | ||
| Line 28: | Line 29: | ||
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
| − | * '' | + | * ''Rst'': asynchronous reset to zero the register |
* ''En'': write enable | * ''En'': write enable | ||
* ''D'': 10-bit data-in bus | * ''D'': 10-bit data-in bus | ||
| Line 40: | Line 41: | ||
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
| − | * '' | + | * ''Rst'': asynchronous reset to zero the register |
* ''En'': write enable | * ''En'': write enable | ||
* ''A'': 3-bit address | * ''A'': 3-bit address | ||
| Line 50: | Line 51: | ||
=== DAC Registers === | === DAC Registers === | ||
| − | A set of 32 | + | A set of 32 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. |
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
| − | * '' | + | * ''Rst'': asynchronous reset to zero the register |
* ''En'': write enable | * ''En'': write enable | ||
| − | * ''A'': 5 | + | * ''A'': 5-bit address |
* ''D'': 14-bit data-in bus | * ''D'': 14-bit data-in bus | ||
outputs | outputs | ||
* ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words) | * ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words) | ||
Revision as of 19:45, 3 June 2008
Registers
State Register
A three-bit register to store the current state. inputs
- Clk: clock
- Rst: asynchronous, reset to zero the register (puts system into reset state)
- En: write enable
- D: three-bit data-in bus
outputs
- Q: three-bit data-out bus
Packet Type Register
An 8-bit register to store the 2nd byte of an accepted packet. inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- D: 8-bit data-in bus
outputs
- Q: 8-bit data-out bus
Temperature Register
A 16-bit register to store the most recent temperature data. inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- D: 10-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 6 zeros to facilitate packaging into 2-byte words)
ADC Registers
A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- A: 3-bit address
- D: 12-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)
DAC Registers
A set of 32 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- A: 5-bit address
- D: 14-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)