Difference between revisions of "FPGA Reset"
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| − | == ( | + | == (00X) Reset Modules == |
| − | Block 000 will have four functional blocks: one each for the DAC, ADC, and | + | The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved) |
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| + | Block 000 will have four functional blocks: one each for the DAC, ADC, and , and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see [[Reset and Initialization]]. | ||
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| − | MAC Address Register Control Lines | + | [[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines |
* ''MACregs_En'': [out] register enable (write) signal | * ''MACregs_En'': [out] register enable (write) signal | ||
* ''MACregs_A'': [out] byte address (4-bit) | * ''MACregs_A'': [out] byte address (4-bit) | ||
Revision as of 18:38, 29 May 2008
(00X) Reset Modules
The reset modules Reset_hard (000) and Reset_soft (001) coordinate various stages of the board reset. The former, analogous to the cold boot of a computer, performs the basic initial reset steps dealing mainly with the startup and configuration of the Ethernet Controller chip (EC). The latter module is a more customized second stage of full reset or just a soft reset that concerns the sensor and DAC chips. It also records the MAC address of the tagger-controlling PC for further communication. (This cannot be handled in the Reset_hard stage as all registers on the EC and FPGA are cleared and the PC's MAC address stamped on the hard reset packet (R-packet) cannot be saved)
Block 000 will have four functional blocks: one each for the DAC, ADC, and , and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see Reset and Initialization.
- Clk: [in] clock
Reset Signals
- Rst: [in] asynchronous reset
- Eth_iRst: [inout] EC active-low reset pin
- Eth_iINT: [in] EC active-low interrupt signal
State Register Control Lines
- state_En: [out] state register enable (write) signal
- state_D: [out] (3-bit) state register input
- state_Q: [in] (3-bit) state register output
MAC Address Register Control Lines
- MACregs_En: [out] register enable (write) signal
- MACregs_A: [out] byte address (4-bit)
- MACregs_D: [out] 8-bit input value
Transceiver Control Lines
- TxRx_Go: [out] "Go" signal to read/write an EC control register byte
- TxRx_Aout: [out] EC control register address (8-bit)
- TxRx_Dout: [out] EC control register write value
- TxRx_RiW: [out] active-high read, active-low write flag
- TxRx_Din: [in] EC control register return value
- TxRx_Done: [in] "Done" signal from Transceiver.
- dbShort: [in] debug signal to bypass EC reset waiting periods