Difference between revisions of "FPGA Reset"

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== (000) Reset Cycle ==
 
== (000) Reset Cycle ==
  
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Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet controller, and one to coordinate their completion.  The temperature sensor lacks an external reset function; it self-initializes on startup.  The "R" packet will supply flags as to whether or not to enable the various blocks.  A power-on reset will default to resetting all components.  Using the enable flags like a mask on the done lines, the fourth functional block will update the state register.  For information on the reset procedures, see [[Reset and Initialization]].
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Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet Controller (EC), and one to coordinate their completion.  The temperature sensor lacks an external reset function; it self-initializes on startup.  The "R" packet will supply flags as to whether or not to enable the various blocks.  A power-on reset will default to resetting all components.  Using the enable flags like a mask on the done lines, the fourth functional block will update the state register.  For information on the reset procedures, see [[Reset and Initialization]].
  
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inputs
 
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* ''Clk'': clock
 
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* ''/Rst'': asynchronous, active-low reset
 
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* ''State'': 3-bit state value
 
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* ''D_En'': DAC enable, assume held high/low by previous block
 
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* ''A_En'': ADC enable, assume held high/low by previous block
 
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* ''E_En'': Ethernet enable, assume held high/low by previous block
 
  
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internal signals
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* ''Clk'': [in] clock
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* ''S_En'': state enable, ''S_En'' <= not (''St(2)'' or ''St(1)'' or ''St(0)'')
 
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* ''Go'': when ''S_En'' goes high ''Go'' pulses for one cycle
 
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* ''D_Go'': DAC reset go pulse, ''D_Go'' <= ''Go'' and ''D_En''
 
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* ''A_Go'': ADC reset go pulse, ''A_Go'' <= ''Go'' and ''A_En''
 
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* ''E_Go'': Ethernet reset go pulse, ''E_Go'' <= ''Go'' and ''E_En''
 
  
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blocks
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* '''DAC Reset'''
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Reset Signals
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** Resets and initializes the DAC.
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* ''Rst: [in] asynchronous reset
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** inputs
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* ''Eth_iRst'': [inout] EC active-low reset pin
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*** ''Clk'': clock
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* ''Eth_iINT'': [in] EC active-low interrupt signal
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*** ''/Rst'': asynchronous, active-low reset
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*** ''D_Go'': go pulse to begin reset/initialization process
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** outputs
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[[FPGA_Register#State_Register|State Register]] Control Lines
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*** - All DAC reset/initialization control lines -
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* ''state_En'': [out] state register enable (write) signal
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*** ''D_Done'': goes high when reset/initialization process is complete, falls on ''D_Go'' pulse
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* ''state_D'': [out] (3-bit) state register input
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* '''ADC Reset'''
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* ''state_Q'': [in] (3-bit) state register output
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** Resets and initializes the ADC.
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** inputs
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*** ''Clk'': clock
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MAC Address Register Control Lines
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*** ''/Rst'': asynchronous, active-low reset
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* ''MACregs_En'': [out] register enable (write) signal
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*** ''A_Go'': go pulse to begin reset/initialization process
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* ''MACregs_A'': [out] byte address (4-bit)
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** outputs
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* ''MACregs_D'': [out] 8-bit input value
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*** - All ADC reset/initialization control lines -
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*** ''A_Done'': goes high when reset/initialization process is complete, falls on ''A_Go'' pulse
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* '''Ethernet Reset'''
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[[FPGA_Transceiver|Transceiver]] Control Lines
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** Resets and initializes the Ethernet controller.
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* ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte
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** inputs
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* ''TxRx_Aout'': [out] EC control register address (8-bit)
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*** ''Clk'': clock
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* ''TxRx_Dout'': [out] EC control register write value
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*** ''/Rst'': asynchronous, active-low reset
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* ''TxRx_RiW'': [out]  active-high read, active-low write flag
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*** ''E_Go'': go pulse to begin reset/initialization process
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* ''TxRx_Din'': [in] EC control register return value
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** outputs
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* ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]].
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*** - All Ethernet reset/initialization control lines -
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*** ''E_Done'': goes high when reset/initialization process is complete, falls on ''E_Go'' pulse
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* ''dbShort'': [in] debug signal to bypass EC reset waiting periods
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* '''Coordinator'''
 
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** Coordinates the completion of each reset cycle and notifies other blocks that the reset process is complete.
 
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** inputs
 
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*** ''Clk'': clock
 
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*** ''/Rst'': asynchronous, active-low reset
 
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*** ''D_En'': high when DAC is to be reset
 
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*** ''D_Done'': high when DAC is done resetting
 
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*** ''A_En'': high when ADC is to be reset
 
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*** ''A_Done'': high when ADC is done resetting
 
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*** ''E_En'': high when Ethernet controller is to be reset
 
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*** ''E_Done'': high when Ethernet controller is done resetting
 
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** internal signals
 
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*** ''Flag'' <= (''D_Done'' or not ''D_En'') and (''A_Done'' or not ''A_En'') and (''E_Done'' or not ''E_En'')
 
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** outputs
 
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*** ''Done'': when ''Flag'' goes high, ''Done'' pulses for one cycle; connects to state register as an enable
 
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*** ''New_St'': new state to be written to the state register; goes to 001 while ''Done'' is high
 

Revision as of 18:25, 29 May 2008

(000) Reset Cycle

Block 000 will have four functional blocks: one each for the DAC, ADC, and Ethernet Controller (EC), and one to coordinate their completion. The temperature sensor lacks an external reset function; it self-initializes on startup. The "R" packet will supply flags as to whether or not to enable the various blocks. A power-on reset will default to resetting all components. Using the enable flags like a mask on the done lines, the fourth functional block will update the state register. For information on the reset procedures, see Reset and Initialization.


  • Clk: [in] clock


Reset Signals

  • Rst: [in] asynchronous reset
  • Eth_iRst: [inout] EC active-low reset pin
  • Eth_iINT: [in] EC active-low interrupt signal


State Register Control Lines

  • state_En: [out] state register enable (write) signal
  • state_D: [out] (3-bit) state register input
  • state_Q: [in] (3-bit) state register output


MAC Address Register Control Lines

  • MACregs_En: [out] register enable (write) signal
  • MACregs_A: [out] byte address (4-bit)
  • MACregs_D: [out] 8-bit input value


Transceiver Control Lines

  • TxRx_Go: [out] "Go" signal to read/write an EC control register byte
  • TxRx_Aout: [out] EC control register address (8-bit)
  • TxRx_Dout: [out] EC control register write value
  • TxRx_RiW: [out] active-high read, active-low write flag
  • TxRx_Din: [in] EC control register return value
  • TxRx_Done: [in] "Done" signal from Transceiver.
  • dbShort: [in] debug signal to bypass EC reset waiting periods
Retrieved from "https://zeus.phys.uconn.edu/wiki/index.php?title=FPGA_Reset&oldid=3530"