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Line 71: − == Registers ==+ − − === State Register === − A three-bit register to store the current state. − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) − * ''En'': write enable − * ''D'': three-bit data-in bus − − outputs − * ''Q'': three-bit data-out bus − − − === Packet Type Register === − An 8-bit register to store the 2nd byte of an accepted packet. − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) − * ''En'': write enable − * ''D'': 8-bit data-in bus − − outputs − * ''Q'': 8-bit data-out bus − − − === Temperature Register === − A 16-bit register to store the most recent temperature data. − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) − * ''En'': write enable − * ''D'': 10-bit data-in bus − − outputs − * ''Q'': 16-bit data-out bus (data pre-padded with 6 zeros to facilitate packaging into 2-byte words) − − − === ADC Registers === − A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) − * ''En'': write enable − * ''A'': 3-bit address − * ''D'': 12-bit data-in bus − − outputs − * ''Q'': 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words) − − − === DAC Registers === − A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. − inputs − * ''Clk'': clock − * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) − * ''En'': write enable − * ''A'': 5/5/4-bit address (currently set at 5-bit) − * ''D'': 14-bit data-in bus − − outputs − * ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words) Line 584:
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Programming the Ethernet controller (view source)
Revision as of 18:54, 16 May 2008
, 18:54, 16 May 2008→Controller
[[FPGA_Transceiver|Transceiver]]
[[FPGA_Transceiver|Transceiver]]
[[FPGA_Registers|Registers]]
== Reusable Components ==
== Reusable Components ==
*** ''Done'': pulse to signal completion
*** ''Done'': pulse to signal completion
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high
*** ''New_St'': 3-bit bus of new state to write to state register; goes to 010 when ''Done'' is high
= Emulator =
= Emulator =