Difference between revisions of "Design and prototyping of SiPM electronics"

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Line 45: Line 45:
 
** <s>Transceiver</s>, extra debugging quasi-emulators in progress
 
** <s>Transceiver</s>, extra debugging quasi-emulators in progress
 
** [[Reset and Initialization|Reset module]]
 
** [[Reset and Initialization|Reset module]]
*** Check all modules for proper async reset support.
+
*** <s>Check all modules for proper async reset support</s>
*** Execute on startup
+
*** <s>Execute on startup</s>
*** Execute on command
+
*** <s>Execute on command</s>
*** Soft reset - <s>load</s> and report MAC and location addresses.
+
*** <s>Soft reset - load and report MAC and location addresses.</s>
  
  

Revision as of 20:46, 14 April 2008

This page is a work in progress. More information will be added as the project progresses.

Internal Links

Analog amplifier

Digital control

Programming our FPGA

VHDL in general

  • VHDL tutorial - a brief guide to VHDL design with a design example; the introduction and core of the tutorial.

To-do list

Ethernet module

  • Complete Ethernet controller module
    • Registers
    • Idler
    • Reader
    • Querier
    • Programmer
    • Transmitter
    • Transceiver, extra debugging quasi-emulators in progress
    • Reset module
      • Check all modules for proper async reset support
      • Execute on startup
      • Execute on command
      • Soft reset - load and report MAC and location addresses.


  • Integrate all modules and simulate the device as a whole
  • Determine size of FPGA
  • Design or purchase connector to bus board
  • Purchase all components (including EEPROM, RJ-45 female jack, etc)
  • Obtain footprints of all chips, connectors, jacks, etc
  • PCB layout
  • Prototype PCB
  • Design bus board
  • Design analog board