461
edits
Changes
Jump to navigation
Jump to search
Line 424:
Line 424: + + + + + + + + + + + +
Programming the Ethernet controller (view source)
Revision as of 20:25, 19 July 2007
, 20:25, 19 July 2007→(110) Program DAC
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Sel'': 5/5/4-bit select bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Data'': 32/24/16-bit data bus to internal registers
*** ''Done'': pulse to signal completion
* '''Discarder'''
** This block orders the CP2200/1 to discard the packet, now that the FPGA is done with all the data contained within the packet.
** inputs
*** ''Clk'': clock
*** ''/Rst'': asynchronous, active-low reset
*** ''Go'': pulse to begin; feeds from ''Done'' signal of Programmer
*** ''TxRx_Done'': ''Done'' signal on transceiver
** outputs
*** ''TxRx_Go'': ''Go'' signal on transceiver
*** ''TxRx_R/W'': ''R/W'' signal on transceiver
*** ''TxRx_A'': ''A_in'' bus on transceiver
*** ''Done'': pulse to signal completion
*** ''Done'': pulse to signal completion
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high
*** ''New_St'': next state to load into the state register; goes to 111 when ''Done'' is high