Difference between revisions of "FPGA Registers"
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=== State Register === | === State Register === | ||
A three-bit register to store the current state. | A three-bit register to store the current state. | ||
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| − | === | + | === MAC Address Registers === |
| − | + | ||
| + | A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules. | ||
| + | |||
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
* ''Rst'': asynchronous reset to zero the register | * ''Rst'': asynchronous reset to zero the register | ||
* ''En'': write enable | * ''En'': write enable | ||
| − | * ''D'': | + | * ''A'': 3-bit address |
| + | * ''D'': 12-bit data-in bus | ||
outputs | outputs | ||
| − | * ''Q'': | + | * ''Q'': 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words) |
=== Temperature Register === | === Temperature Register === | ||
| − | A | + | |
| + | A 10-bit register to store the most recent temperature data. A 16-bit word is actually returned for the convenience of other modules - the 10-bit value is pre-padded with zeros. | ||
| + | |||
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
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=== ADC Registers === | === ADC Registers === | ||
| − | A set of eight | + | |
| + | A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules. | ||
| + | |||
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
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=== DAC Registers === | === DAC Registers === | ||
| − | A set of 32 | + | A set of 32 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules. |
inputs | inputs | ||
* ''Clk'': clock | * ''Clk'': clock | ||
Revision as of 23:37, 6 June 2008
State Register
A three-bit register to store the current state. inputs
- Clk: clock
- Rst: asynchronous, reset to zero the register (puts system into reset state)
- En: write enable
- D: three-bit data-in bus
outputs
- Q: three-bit data-out bus
MAC Address Registers
A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules.
inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- A: 3-bit address
- D: 12-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)
Temperature Register
A 10-bit register to store the most recent temperature data. A 16-bit word is actually returned for the convenience of other modules - the 10-bit value is pre-padded with zeros.
inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- D: 10-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 6 zeros to facilitate packaging into 2-byte words)
ADC Registers
A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules.
inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- A: 3-bit address
- D: 12-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words)
DAC Registers
A set of 32 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules. inputs
- Clk: clock
- Rst: asynchronous reset to zero the register
- En: write enable
- A: 5-bit address
- D: 14-bit data-in bus
outputs
- Q: 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words)