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SiPM digital control board netlist (view source)
Revision as of 20:07, 24 June 2008
, 20:07, 24 June 2008→Configuration Pins: modified connections to reflect suggested connections in EEPROM spec sheet
|DONE
|DONE
|Programming complete pin
|Programming complete pin
|FPGA programmer
|XCF01S CE, pin 10
|FPGA programmer
|XCF01S CE, pin 10
|Goes high when programming is complete
|Goes high when programming is complete
|----
|----
|PROG_B
|PROG_B
|Initiates programming process
|Initiates programming process
|FPGA programmer
|XCF01S CF, pin 7
|FPGA programmer
|XCF01S CF, pin 7
|Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation
|Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation
|----
|----
|CCLK
|CCLK
|Clock for programming
|Clock for programming
|XCF01S clock input pin
|XCF01S CLK, pin 3
|User I/O
|User I/O
|If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input
|If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input
|INIT_B
|INIT_B
|Programming status indicator
|Programming status indicator
|FPGA programmer
|XCF01S OE/RESET, pin 8
|User I/O, or high or low
|User I/O, or high or low
|Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error<br>After programming, should be driven high or <br>low if not used for user I/O
|Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error<br>After programming, should be driven high or <br>low if not used for user I/O