Changes

= (011) Read Packet =

= (011) Read Packet =

This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the [[Ethernet_packets|packet type]] is invalid. Otherwise it will yield control to the module relevant to the packet type. This selection is diagrammed in the adjacent figure.

This block performs the initial reading of the packet. It skips through the packet header and reads the first two bytes of the payload, which contain the target location and packet type. (The latter is not to be confused with the packet type specified in the packet header. Our packets have a separate branding convention.) Based on these, the module will reject the packet (request a "skip" of the packet in the receive FIFO buffer) if the packet's contents will not be necessary further. The Reader will return control to the [[FPGA_Idler|Idler (010)]] if the packet is not addressed to its location or the [[Ethernet_packets|packet type]] is invalid. Otherwise it will yield control to the module relevant to the packet type. This selection is diagrammed in the adjacent figure.

As implied in the diagram, packet types R and Q (Reset and Query respectively) do no carry any data for the FPGA: their role is to order reset or request feedback from the sensor chips. Soft Reset and Programmer, on the other hand require certain reset/configuration data and DAC voltage values respectively, so these packets are kept. (It becomes the responsibility of these modules to dismiss these packets when finished.)

As implied in the diagram, packet types R and Q (Reset and Query respectively) do no carry any data for the FPGA: their role is to order reset or request feedback from the sensor chips. Soft Reset and Programmer, on the other hand require certain reset/configuration data and DAC voltage values respectively, so these packets are kept. (It becomes the responsibility of these modules to dismiss these packets when finished.)

== Programming Details ==

== Programming Details ==

The module is implemented as a counter of bytes read with the auto-read interface of the Ethernet Controller chip (EC) starting from the beginning of the header. ''AutoRd'' module is instantiated and is pulsed on each counter click. Upon reading the 15th, the location is checked for match to the board slot's hardwired location (''LocStamp'' port listed below). Upon the 16th byte, the packet type is checked. Packet rejection (skipping in the receive buffer) if performed by writing "00000010" to RXCN (0x11) control register. (See the CP220x manual for more information.) ''wrToAddr'' module is instantiated and is pulsed by the Discard signal which may be turned high at any point of the selection process.  

The module is implemented as a counter of bytes read with the auto-read interface of the Ethernet Controller chip (EC) starting from the beginning of the header. ''AutoRd'' module is instantiated and is pulsed on each counter click. Upon reading the 15th, the location is checked for match to the board slot's hardwired location (''LocStamp'' port listed below). Upon the 16th byte, the packet type is checked. Packet rejection (skipping in the receive buffer) if performed by writing "00000010" to RXCN (0x11) control register. (See the CP220x manual for more information.) ''wrToAddr'' module is instantiated and is pulsed by the Discard signal which may be turned high at any point of the selection process.