Changes

This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information.

This communication standard calls for a bridge module that communicates with the EC upon request from other modules. A "[[FPGA_Transceiver|Transceiver]]" was designed for this purpose. It abstracts the communication with the EC as well as the clock frequency difference. This module in fact subdivides the main 20 MHz; clock to generate the "slow" 5 MHz clock for the rest of the FPGA. Please refer to the [[FPGA_Transceiver|detailed page]] on the Transceiver for more information.