Difference between revisions of "VHDL tutorial"

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! colspan="2" style="background:#ffff66" | VHDL Tutorial
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| colspan="2" style="background:#ffff99" | A brief guide to VHDL design with a design example; the introduction and core of the tutorial.
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| style="background:#ffff66" | < prev
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| style="background:#ffff66" | [[VHDL: Where to start|next >]]
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FPGA programming using a hardware description language is not a commonly taught skill in physics programs, but is a necessary skill for designing the electronics required for this project.  This tutorial aims to layout the design process and teach the basics of hardware description language; in particular [http://en.wikipedia.org/wiki/Vhdl VHDL].  The main competitor to VHDL is [http://en.wikipedia.org/wiki/Verilog Verilog]; tutorials and information regarding Verilog can be found through Google web searching.
 
FPGA programming using a hardware description language is not a commonly taught skill in physics programs, but is a necessary skill for designing the electronics required for this project.  This tutorial aims to layout the design process and teach the basics of hardware description language; in particular [http://en.wikipedia.org/wiki/Vhdl VHDL].  The main competitor to VHDL is [http://en.wikipedia.org/wiki/Verilog Verilog]; tutorials and information regarding Verilog can be found through Google web searching.
  
 
== Design example ==
 
== Design example ==
  
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To illustrate the discussions in this tutorial, a design example is discussed along the way.  The design example is the [[http://zeus.phys.uconn.edu/wiki/index.php?title=Programming_the_FPGA#Emulator_.28D.29|emulator for the AD5535 DAC]].  As each step of the design process is discussed, the DAC emulator will be used for illustration.
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To illustrate the discussions in this tutorial, a design example is discussed along the way.  The design example is the [[Programming_the_DAC#Emulator|emulator for the AD5535 DAC]].  As each step of the design process is discussed, the DAC emulator will be used for illustration.
  
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== Where to start ==
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== The tutorial ==
  
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The first part of the design process is completely independent of any code.  The first step is to define the "black box" of your circuit; that is, draw a box and say what goes in and what comes out.  VHDL allows three types of ''pins'' (connections to the outside world):
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Due to the length of the tutorial, it had to be broken into several pages.  Here are the links to the various sections of the tutorial.  The first three sections discuss VHDL itself.  The final section is about using the development environment provided by Xilinx; you can read this section first or last as you see fit.
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* '''in''': An ''in'' pin can be read from but never written to.
 
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* '''out''': An ''out'' pin can be written to but never read from.
 
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* '''inout''': An ''inout'' pin can be both read from and written to, providing the flexibility to allow bidirectional communication on a single line.  At first this seems the ideal choice and that you would always want inout pins; in actual fact you want to avoid inout pins unless you absolutely need them for bidirectional communication.
 
  
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* [[VHDL: Where to start]] - Section one of the tutorial, focusing on preparing your design for coding.
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* [[VHDL: Enter the code monkey]] - Section two of the tutorial, focusing on outlining the framework of your code.
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:''See also: [http://en.wikipedia.org/wiki/Code_monkey code monkey]''
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* [[VHDL: The real code]] - Section three of the tutorial, focusing on coding the body of your design.
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* [[VHDL: Xilinx ISE]] - Section four of the tutorial, focusing on using the development environment.
  
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== Extras ==
  
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Having defined your block box, you need to fill in your black box.
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Here is some extra information regarding VHDL to be used as reference material.
  
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=== VHDL Resolution Table ===
  
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VHDL STD_LOGIC and STD_LOGIC_VECTOR both operate on 9-value logic defined by IEEE.  The nine states are:
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* U: uninitialized
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* X: forcing unknown
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* 0: forcing 0
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* 1: forcing 1
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* Z: high impedance
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* W: weak unknown
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* L: weak 0
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* H: weak 1
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* &#8211;: don't care
  
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== VHDL Resolution Table ==
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If you have two or more drivers for the same line, then VHDL must somehow resolve the conflict.  The resolution table is given below.
  
 
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|+VHDL Resolution Table
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|+ '''VHDL Resolution Table'''
 
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!  !! U !! X !! 0 !! 1 !! Z !! W !! L !! H !! -
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!  !! U !! X !! 0 !! 1 !! Z !! W !! L !! H !! &#8211;
 
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! U
 
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| U || X || 0 || 1 || H || W || W || H || X
 
| U || X || 0 || 1 || H || W || W || H || X
 
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! &#8211;
 
| U || X || X || X || X || X || X || X || X
 
| U || X || X || X || X || X || X || X || X
 
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VHDL Logic States
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=== Links ===
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* U: uninitialized
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* X: forcing unknown
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In case you can't follow the near-incoherent ramblings that constitute my tutorial, here are links to some others.  And always remember: Google is a programmer's best friend.
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* 0: forcing 0
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* http://esd.cs.ucr.edu/labs/tutorial/
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* 1: forcing 1
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* http://www.vhdl-online.de/tutorial/
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* Z: high impedance
 
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* W: weak unknown
 
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* L: weak 0
 
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* H: weak 1
 
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* -: don't care
 

Latest revision as of 18:55, 17 July 2007

VHDL Tutorial
A brief guide to VHDL design with a design example; the introduction and core of the tutorial.
< prev next >

FPGA programming using a hardware description language is not a commonly taught skill in physics programs, but is a necessary skill for designing the electronics required for this project. This tutorial aims to layout the design process and teach the basics of hardware description language; in particular VHDL. The main competitor to VHDL is Verilog; tutorials and information regarding Verilog can be found through Google web searching.

Design example

To illustrate the discussions in this tutorial, a design example is discussed along the way. The design example is the emulator for the AD5535 DAC. As each step of the design process is discussed, the DAC emulator will be used for illustration.

The tutorial

Due to the length of the tutorial, it had to be broken into several pages. Here are the links to the various sections of the tutorial. The first three sections discuss VHDL itself. The final section is about using the development environment provided by Xilinx; you can read this section first or last as you see fit.

See also: code monkey
  • VHDL: The real code - Section three of the tutorial, focusing on coding the body of your design.
  • VHDL: Xilinx ISE - Section four of the tutorial, focusing on using the development environment.

Extras

Here is some extra information regarding VHDL to be used as reference material.

VHDL Resolution Table

VHDL STD_LOGIC and STD_LOGIC_VECTOR both operate on 9-value logic defined by IEEE. The nine states are:

  • U: uninitialized
  • X: forcing unknown
  • 0: forcing 0
  • 1: forcing 1
  • Z: high impedance
  • W: weak unknown
  • L: weak 0
  • H: weak 1
  • –: don't care

If you have two or more drivers for the same line, then VHDL must somehow resolve the conflict. The resolution table is given below.

VHDL Resolution Table
U X 0 1 Z W L H –
U U U U U U U U U U
X U X X X X X X X X
0 U X 0 X 0 0 0 0 X
1 U X X 1 1 1 1 1 X
Z U X 0 1 Z W L H X
W U X 0 1 W W W W X
L U X 0 1 L W L W X
H U X 0 1 H W W H X
– U X X X X X X X X

Links

In case you can't follow the near-incoherent ramblings that constitute my tutorial, here are links to some others. And always remember: Google is a programmer's best friend.

Retrieved from "https://zeus.phys.uconn.edu/wiki/index.php?title=VHDL_tutorial&oldid=2102"