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SiPM Amplifier Optimization (view source)
Revision as of 21:42, 16 October 2011
, 21:42, 16 October 2011→Gain
The amplifier provided by Photonique with a gain of roughly 3 kΩ was well suited for single photon counting. However, for typical signals ranging in the hundreds of SiPM pixels, this gain excessive. However, the option of switching back to single photon detection for the purposes of calibration would be a nice feature.
The amplifier provided by Photonique with a gain of roughly 3 kΩ was well suited for single photon counting. However, for typical signals ranging in the hundreds of SiPM pixels, this gain excessive. However, the option of switching back to single photon detection for the purposes of calibration would be a nice feature.
From the perspective of expected signal amplitudes (taking into account optical and SiPM's quantum efficiencies) signals around 300 pixels (px) are expected. With a SiPM gain of about 2 × 10<sup>5</sup> ~ 9.6 pC are expected to be deposited. Design uncertainties that go into the full calculation summarized here can easily allow variation in this result by a factor of two or more. Roughly estimating this charge to be contained in a triangular pulse with 5 ns FWHM (after all the broadening inherent in the amplifier) yields a total signal peak of 0.5 mA. With this figure and the full range of the ADC (2V) it seems that 3 kΩ is still appropriate. However this does not leave room for variation discussed above. Instead, a goal of sub-1 kΩ gain was adopted.
From the perspective of expected signal amplitudes (taking into account optical and SiPM's quantum efficiencies) signals around 300 pixels (px) are expected. With a SiPM gain of about 2 × 10<sup>5</sup> ~ 9.6 pC are expected to be deposited. Design uncertainties that go into the full calculation summarized here can easily allow variation in this result by a factor of two or more. Roughly estimating this charge to be contained in a triangular pulse with <strike>5 ns</strike> 20 ns? FWHM (after all the broadening inherent in the amplifier) yields a total signal peak of 0.5 mA. With this figure and the full range of the ADC (2V) it seems that 3 kΩ is still appropriate. However this does not leave room for variation discussed above. Instead, a goal of sub-1 kΩ gain was adopted.
For the high gain setting, the issue is mainly the vertical resolution of the ADC. For most of the duration of this project, the 8-bit version of the ADC was planned to be allocated for microscope readout, imposing a stringent requirement on gain in order to avoid the digitization noise inherent in signals only a few adc voltage steps. The 12-bit ADC makes clean readout of single pixel wavefunctions more realistic: at the most sensitive scale of 0.5 V, the resolution is 0.12 mV. However, we must also take into account noise and a possible factor of two loss in the split of the signal between the ADC and the CFD (constant fraction discriminator to prepare for time pick-off.) This time, it is appropriate to take a pessimistic scenario of the pulse shape: taking a triangular pulse with 30 ns FWHM, leading to a single pixel current peak of 0.27 μA. Under these conditions, gain of 7 kΩ is enough, giving 15 adc steps per pixel.
For the high gain setting, the issue is mainly the vertical resolution of the ADC. For most of the duration of this project, the 8-bit version of the ADC was planned to be allocated for microscope readout, imposing a stringent requirement on gain in order to avoid the digitization noise inherent in signals only a few adc voltage steps. The 12-bit ADC makes clean readout of single pixel wavefunctions more realistic: at the most sensitive scale of 0.5 V, the resolution is 0.12 mV. However, we must also take into account noise and a possible factor of two loss in the split of the signal between the ADC and the CFD (constant fraction discriminator to prepare for time pick-off.) This time, it is appropriate to take a pessimistic scenario of the pulse shape: taking a triangular pulse with 30 ns FWHM, leading to a single pixel current peak of 0.27 μA. Under these conditions, gain of 7 kΩ is enough, giving 15 adc steps per pixel.
=== Minimal Dependence on <math>\beta</math> ===
=== Minimal Dependence on <math>\beta</math> ===
=== Short Pulses ===
=== Short Pulses ===
The duration of the amplified signals is, in essence, the dead time of the channel. (Pulses with significant overlap are difficult to distinguish.) The lower bound of the pulse width is set by the scintillator. The BCF-20 intended for use in the microscope has a decay time of 2.7 ns. A somewhat stricter restriction is set by the sampling rate of the ADC - 250 MHz. A rough (and vague) guideline of 15 total signal duration has been observed during the design.
The duration of the amplified signals is, in essence, the dead time of the channel. (Pulses with significant overlap are difficult to distinguish.) The lower bound of the pulse width is set by the scintillator. The BCF-20 intended for use in the microscope has a decay time of 2.7 ns. A somewhat stricter restriction is set by the sampling rate of the ADC - 250 MHz. A rough (and vague) guideline of 15 ns total signal duration has been observed during the design.
=== Power Consumption ===
=== Power Consumption ===
[[Image:AmpVis_v6_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and Ω are implied unless corrected by different prefix.]]
[[Image:AmpCircuit_v7_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and Ω are implied unless corrected by different prefix.]]
It essential to avoid clipping the signal at designed gain levels and to be able to utilize the full range (2 V) of the ADC. Appropriate DC level were set to avoid saturation any transistor collectors. This turns out a bit involved, since the collector-base voltage (plus the canonical saturation margin of 100 mV) gap necessary is more than the maximum desired signal of 2 V due to attenuation along the amplifier chain. Changing DC levels changes biasing of transistor bases, changing the quiescent current and therefore the attenuation. Additionally the power budget significantly restricts the DC levels of the circuit.
It essential to avoid clipping the signal at designed gain levels and to be able to utilize the full range (2 V) of the ADC. Appropriate DC level were set to avoid saturation any transistor collectors. This turns out a bit involved, since the collector-base voltage (plus the canonical saturation margin of 100 mV) gap necessary is more than the maximum desired signal of 2 V due to attenuation along the amplifier chain. Changing DC levels changes biasing of transistor bases, changing the quiescent current and therefore the attenuation. Additionally the power budget significantly restricts the DC levels of the circuit.
In the current stage of the design, full 2V range has not been achieved. Both single channel and summing outputs ago up to about 1.5 V.
In the current stage of the design, full 2V range has not been achieved. Both single channel and summing outputs go up to about 1.5 V.
==== The Gain Switch ====
==== The Gain Switch ====
A MOSFET switch the effective collector resistor in the first stage of the summing circuit between about 3 kΩ due to R<sub>e</sub> alone and the parallel path of 165 Ω. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3 V (max: -4 V). Putting its source on the supply rail and switching the gate between 5 V (on) and 0 V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.
A MOSFET switches the effective collector resistance in the first stage of the summing circuit between about 3.3 kΩ due to R<sub>e</sub> alone and about 80 Ω for the parallel path. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3 V (max: -4 V). Putting its source on the supply rail and switching the gate between 5 V (on) and 0 V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.
==== Final Performance Parameters ====
==== Final Performance Parameters ====
With the final parameters specified by the circuit model resistor input vector set to
With the final parameters specified by the circuit model resistor input vector set to
<pre>R = [.56 1 .33 .47 1.36 1 .12 1.22 .1 .082 3.3 .68 .56 .18 2 .392 .7]</pre>
<pre>R = [.56 1 .33 .47 1.36 1 .12 1.22 .1 .082 3.3 .15 .68 .18 2 .392 .7 1]*1e3</pre>
(see [[SiPM Amplifier Components]] for a complete list of component values) the following theoretical specifications are achieved:
(see [[SiPM Amplifier Components]] for a complete list of component values) the following theoretical specifications are achieved:
{| style="text-align:center" cellpadding="3"
{| align="center" style="text-align:center" cellpadding="4"
! !! Amplifier Stage !! Summing Stage !! Units !! Comments
! !! Amplifier Stage !! Summing Stage !! Units !! Notes
|-
|-
! align="left" | Gain (low/high)
! align="left" | Gain (low/high)
| 0.29 || 0.29/7.5 || kΩ
| 0.29 || 0.29/7.5 || kΩ || 50 Ω load assumed
|-
|-
! align="left" | Input impedance
! align="left" | Input impedance
| 13.5 || 27.3 || Ω
| 13.5 || 27.3 || Ω
|-
|-
! align="left" | Power
! align="left" | Power (quiescent)
| 42 || 47 || mW || i.e. 52 mW/channel
| 42 || 47 || mW || i.e. 52 mW/channel
|-
|-
! align="left" | Dynamic Range
! align="left" | Output pulse height (max)
| 1.46 || 1.45 || V
| 1.46 || 1.45 || V
|}
|}