Changes

# adjustable gain, ranging from readout of hundreds of pixels to calibration with single-photon counting

# adjustable gain, ranging from readout of hundreds of pixels to calibration with single-photon counting

# less than 15% gain variability on transistor <math>\beta</math> (<math>h_{FE}</math>) parameter  

# less than 15% gain variability on transistor <math>\beta</math> (<math>h_{FE}</math>) parameter  

# summing circuit to pool SiPM signals in groups of 5 (readout of individual channels must not affect readout of the some regardless of termination used)

# summing circuit to pool SiPM signals in groups of 5 (readout of individual channels must not affect readout of the sum regardless of termination used)

# minimized pulse duration for higher running rates

# minimized pulse duration for higher running rates

# minimized power consumption

# minimized power consumption

The amplifier provided by Photonique with a gain of roughly 3&nbsp;k&Omega; was well suited for single photon counting. However, for typical signals ranging in the hundreds of SiPM pixels, this gain excessive. However, the option of switching back to single photon detection for the purposes of calibration would be a nice feature.  

The amplifier provided by Photonique with a gain of roughly 3&nbsp;k&Omega; was well suited for single photon counting. However, for typical signals ranging in the hundreds of SiPM pixels, this gain excessive. However, the option of switching back to single photon detection for the purposes of calibration would be a nice feature.  

From the perspective of expected signal amplitudes (taking into account optical and SiPM's quantum efficiencies) signals around 300 pixels (px) are expected. With a SiPM gain of about 2&nbsp;&times;&nbsp;10⁵ ~ 9.6&nbsp;pC are expected to be deposited. Design uncertainties that go into the full calculation summarized here can easily allow variation in this result by a factor of two or more. Roughly estimating this charge to be contained in a triangular pulse with 5&nbsp;ns FWHM (after all the broadening inherent in the amplifier) yields a total signal peak of 0.5&nbsp;mA. With this figure and the full range of the ADC (2V) it seems that 3&nbsp;k&Omega; is still appropriate. However this does not leave room for variation discussed above. Instead, a goal of sub-1&nbsp;k&Omega; gain was adopted.

From the perspective of expected signal amplitudes (taking into account optical and SiPM's quantum efficiencies) signals around 300 pixels (px) are expected. With a SiPM gain of about 2&nbsp;&times;&nbsp;10⁵ ~ 9.6&nbsp;pC are expected to be deposited. Design uncertainties that go into the full calculation summarized here can easily allow variation in this result by a factor of two or more. Roughly estimating this charge to be contained in a triangular pulse with <strike>5&nbsp;ns</strike> 20&nbsp;ns? FWHM (after all the broadening inherent in the amplifier) yields a total signal peak of 0.5&nbsp;mA. With this figure and the full range of the ADC (2V) it seems that 3&nbsp;k&Omega; is still appropriate. However this does not leave room for variation discussed above. Instead, a goal of sub-1&nbsp;k&Omega; gain was adopted.

For the high gain setting, the issue is mainly the vertical resolution of the ADC. For most of the duration of this project, the 8-bit version of the ADC was planned to be allocated for microscope readout, imposing a stringent requirement on gain in order to avoid the digitization noise inherent in signals only a few adc voltage steps. The 12-bit ADC makes clean readout of single pixel wavefunctions more realistic: at the most sensitive scale of 0.5&nbsp;V, the resolution is 0.12&nbsp;mV. However, we must also take into account noise and a possible factor of two loss in the split of the signal between the ADC and the CFD (constant fraction discriminator to prepare for time pick-off.) This time, it is appropriate to take a pessimistic scenario of the pulse shape: taking a triangular pulse with 30&nbsp;ns FWHM, leading to a single pixel current peak of 0.27&nbsp;&mu;A. Under these conditions, gain of 7&nbsp;k&Omega; is enough, giving 15 adc steps per pixel.

For the high gain setting, the issue is mainly the vertical resolution of the ADC. For most of the duration of this project, the 8-bit version of the ADC was planned to be allocated for microscope readout, imposing a stringent requirement on gain in order to avoid the digitization noise inherent in signals only a few adc voltage steps. The 12-bit ADC makes clean readout of single pixel wavefunctions more realistic: at the most sensitive scale of 0.5&nbsp;V, the resolution is 0.12&nbsp;mV. However, we must also take into account noise and a possible factor of two loss in the split of the signal between the ADC and the CFD (constant fraction discriminator to prepare for time pick-off.) This time, it is appropriate to take a pessimistic scenario of the pulse shape: taking a triangular pulse with 30&nbsp;ns FWHM, leading to a single pixel current peak of 0.27&nbsp;&mu;A. Under these conditions, gain of 7&nbsp;k&Omega; is enough, giving 15 adc steps per pixel.

=== Minimal Dependence on <math>\beta</math> ===

=== Minimal Dependence on <math>\beta</math> ===

=== Short Pulses ===

=== Short Pulses ===

The duration of the amplified signals is, in essence, the dead time of the channel. (Pulses with significant overlap are difficult to distinguish.) The lower bound of the pulse width is set by the scintillator. The BCF-20 intended for use in the microscope has a decay time of 2.7&nbsp;ns. A somewhat stricter restriction is set by the sampling rate of the ADC - 250&nbsp;MHz. A rough (and vague) guideline of 15&nbsp; total signal duration has been observed during the design.

The duration of the amplified signals is, in essence, the dead time of the channel. (Pulses with significant overlap are difficult to distinguish.) The lower bound of the pulse width is set by the scintillator. The BCF-20 intended for use in the microscope has a decay time of 2.7&nbsp;ns. A somewhat stricter restriction is set by the sampling rate of the ADC - 250&nbsp;MHz. A rough (and vague) guideline of 15&nbsp;ns total signal duration has been observed during the design.

 

=== Power Consumption ===

=== Power Consumption ===

The low impedance input stage was retained from the earlier design and applied the the summing circuit, since it pools currents from the individual amplifiers. In Photonique's design, the input signal sees the transistor base, base-biasing resistor, and a feedback resistor in parallel. The new input stages take the signal on the emitter (base held at a set DC value), in which case the signal sees the emitter resistor and the impedance looking into the emitter in parallel with each other. The latter dominates with an effective resistance of order 25&nbsp;&Omega;. The input stages are biased with generous amount of current to keep this value low.

The low impedance input stage was retained from the earlier design and applied the the summing circuit, since it pools currents from the individual amplifiers. In Photonique's design, the input signal sees the transistor base, base-biasing resistor, and a feedback resistor in parallel. The new input stages take the signal on the emitter (base held at a set DC value), in which case the signal sees the emitter resistor and the impedance looking into the emitter in parallel with each other. The latter dominates with an effective resistance of order 25&nbsp;&Omega;. The input stages are biased with generous amount of current to keep this value low.

==== <math>\beta</math>-dependence and Voltage Buffering ====

==== <math>\beta</math>-dependence and Voltage Buffering ====

To keep single channel and summing circuit readout independent of each other, a separate driver for the summing circuit was added. The first stage of the amplifier contains a switchable collector resistance which, the ratio of which with the effective resistance of the driver sets the additional gain sought at this stage. The additional inversion (to a positive-going signal) must be countered with another inverter, followed by the voltage buffer similar to that at the end of the single channel amplifier circuit.

To keep single channel and summing circuit readout independent of each other, a separate driver for the summing circuit was added. The first stage of the amplifier contains a switchable collector resistance which, the ratio of which with the effective resistance of the driver sets the additional gain sought at this stage. The additional inversion (to a positive-going signal) must be countered with another inverter, followed by the voltage buffer similar to that at the end of the single channel amplifier circuit.

Signal buffering turns out to be tricky in this project. The requirement of negative output pulse polarity set by the ADC mandates a PNP transistor for the final stages of both amplifier and summing segments. However, the &beta; characteristics of the only acceptable fast PNP found on the market (BFT92W) are even worse than those in its NPN counterpart. The typical value of <math>h_{FE}</math> is 50 with a minimum value of 20, compared to BFR92P from Infineon, which sports values from 70 to near 100. The effective load of the terminators of about &beta;50&nbsp;&Omega remains comparable to the source impedance of the circuit. In other words, the source impedance cannot be considered negligible compared to the load, creating an effective voltage divider whose ration depends on beta! Since the output from the summing circuit suffers from about twice as much variation due to &beta; because of all the preceding stages, a stiffer buffer became essential on this end. The emitter-follower driver was doubled, effectively multiply the &beta;'s of the two transistors. The resulting two diode drops, too low to avoid significant saturation on collectors of earlier stages, are countered with a DC level shift with AC coupling from preceding circuit elements.

Signal buffering turns out to be tricky in this project. The requirement of negative output pulse polarity set by the ADC mandates a PNP transistor for the final stages of both amplifier and summing segments. However, the &beta; characteristics of the only acceptable fast PNP found on the market (BFT92W) are even worse than those in its NPN counterpart. The typical value of <math>h_{FE}</math> is 50 with a minimum value of 20, compared to BFR92P from Infineon, which sports values from 70 to near 100. The effective load of the terminators of about &beta;50&nbsp;&Omega; remains comparable to the source impedance of the circuit. In other words, the source impedance cannot be considered negligible compared to the load, creating an effective voltage divider whose ratio depends on beta! Since the output from the summing circuit suffers from about twice as much variation due to &beta; because of all the preceding stages, a stiffer buffer became essential on this end. The emitter-follower driver was doubled, effectively multiply the &beta;'s of the two transistors. The resulting two diode drops, too low to avoid significant saturation on collectors of earlier stages, are countered with a DC level shift with AC coupling from preceding circuit elements.

 

 

 

 

 

 

It essential to avoid clipping the signal at designed gain levels and to be able to utilize the full range (2&nbsp;V) of the ADC. Appropriate DC level were set to avoid saturation any transistor collectors. This turns out a bit involved, since the collector-base voltage (plus the canonical saturation margin of 100&nbsp;mV) gap necessary is more than the maximum desired signal of 2&nbsp;V due to attenuation along the amplifier chain. Changing DC levels changes biasing of transistor bases, changing the quiescent current and therefore the attenuation. Additionally the power budget significantly restricts the DC levels of the circuit.  

[[Image:AmpVis_v6_DC.png|frame|center|DC characteristics of the amplifier. Units of V, mA, and &Omega; are implied unless corrected by different prefix.]]

In the current stage of the design, full 2V range has not been achieved. Both single channel and summing outputs go up to about 1.5&nbsp;V.

==== The Gain Switch ====

==== The Gain Switch ====

A MOSFET switch the effective collector resistor in the first stage of the summing circuit between about 3&nbsp;k&Omega; due to R_e alone and the parallel path of 165&nbsp;&Omega;. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3&nbsp;V (max: -4&nbsp;V). Putting its source on the supply rail and switching the gate between 5&nbsp;V (on) and  0&nbsp;V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.

A MOSFET switches the effective collector resistance in the first stage of the summing circuit between about 3.3&nbsp;k&Omega; due to R_e alone and about 80&nbsp;&Omega; for the parallel path. NXP's BF1108R has been selected for prototyping. Its typical <math>V_{GS}</math> for current pinch-off is -3&nbsp;V (max: -4&nbsp;V). Putting its source on the supply rail and switching the gate between 5&nbsp;V (on) and  0&nbsp;V (off). A bypass capacitor (not shown in diagram) near the gate lead is important to prevent spurious switching.