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Line 528: − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + Line 842:
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Digital control board documentation (view source)
Revision as of 20:22, 20 August 2010
, 20:22, 20 August 2010→Channel Descriptions
| '''Description'''
| '''Description'''
|-
|-
| P1 || FPGA/TMS ||
| P1 || FPGA/TMS || [JTAG]
| JTAG
| JTAG
|-
|-
| P2
| P2 || FPGA/TDI || [JTAG]
| FPGA/TDI
| JTAG
| JTAG
|-
|-
| P3
| P3 || AD7928/CS || SPI_A_iCS
| AD7928/CS
| SPI chip select for ADC
| SPI chip select for ADC
|-
|-
| P4
| P4 || SPI || SPI_SDI
| SPI
| '''Corrected
| '''Erroneously wired SPI bus trace'''<br>Connects to SDO on temp. sensor and DIN on ADC
|-
|-
| P5
| P5 || CLK_5MHZ || SPI_SCLK
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
|-
| P6
| P6 || No connection ||
| No connection
|
|
|-
|-
| P7
| P7 || No connection ||
| No connection
|
|
|-
|-
| P8
| P8 || DGND ||
| DGND
|
|
|-
|-
| P9
| P9 || No connection ||
| No connection
|
|
|-
|-
| P10
| P10 || No connection ||
| No connection
|
|
|-
|-
| P11
| P11 || +3.3V ||
| +3.3V
|
|
|-
|-
| P12
| P12 || No connection ||
| No connection
|
|
|-
|-
| P13
| P13 || No connection ||
| No connection
|
|
|-
|-
| P14
| P14 || DGND ||
| DGND
|
|
|-
|-
| P15
| P15 || No connection ||
| No connection
|
|
|-
|-
| P16
| P16 || No connection ||
| No connection
|
|
|-
|-
| P17
| P17 || +1.2V ||
| +1.2V
|
|
|-
|-
| P18
| P18 || DGND ||
| DGND
|
|
|-
|-
| P19
| P19 || dBinfo_Start ||
| No connection
|
|
|-
|-
| P20
| P20 || dBinfo_Stream ||
| No connection
|
|
|-
|-
| P21
| P21 || No connection ||
| No connection
|
|
|-
|-
| P22
| P22 || +3.3V ||
| +3.3V
|
|
|-
|-
| P23
| P23 || DGND || [M1: JTAG prog. config.]
| DGND
|
|
|-
|-
| P24
| P24 || DGND || [M2: JTAG prog. config.]
| DGND
|
|
|-
|-
| P25
| P25 || DGND || [M0: JTAG prog. config.]
| DGND
|
|
|-
|-
| P26
| P26 || +3.3V ||
| +3.3V
|
|
|-
|-
| P27
| P27 || FPGA/CLK_IN || fClk
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
| 20 MHz clock input from crystal oscillator
|-
|-
| P28
| P28 || No connection ||
| No connection
|
|
|-
|-
| P29
| P29 || No connection || (db) state_Q(0)
| No connection
|
|
|-
|-
| P30
| P30 || No connection ||
| No connection
|
|
|-
|-
| P31
| P31 || No connection || (db) state_Q(1)
| No connection
|
|
|-
|-
| P32
| P32 || No connection ||
| No connection
|
|
|-
|-
| P33
| P33 || No connection || (db) state_Q(2)
| No connection
|
|
|-
|-
| P34
| P34 || No connection ||
| No connection
|
|
|-
|-
| P35
| P35 || CP2201/INT || Eth_iINT
| CP2201/INT
| Ethernet controller interrupt
| Ethernet controller interrupt
|-
|-
| P36
| P36 || MASTER_RESET || Rst
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
|-
| P37
| P37 || (manually wired) || fClk_out
| No connection
|
|
|-
|-
| P38
| P38 || +1.2V ||
| +1.2V
|
|
|-
|-
| P39
| P39 || No connection ||
| No connection
|
|
|-
|-
| P40
| P40 || CP2201/CS || iCS
| CP2201/CS
| Chip select for ethernet controller
| Chip select for ethernet controller
|-
|-
| P41
| P41 || CP2201/WR || iWR
| CP2201/WR
| Write enable for ethernet controller
| Write enable for ethernet controller
|-
|-
| P42
| P42 || DGND ||
| DGND
|
|
|-
|-
| P43
| P43 || CP2201/RD || iRD
| CP2201/RD
| Read enable for ethernet controller
| Read enable for ethernet controller
|-
|-
| P44
| P44 || CP2201/ALE || ALE
| CP2201/ALE
| Address line enable for ethernet controller
| Address line enable for ethernet controller
|-
|-
| P45
| P45 || +3.3V ||
| +3.3V
|
|
|-
|-
| P46
| P46 || CP2201/RESET || Eth_iRst
| CP2201/RESET
| Reset pin for ethernet controller
| Reset pin for ethernet controller
|-
|-
| P47
| P47 || DGND ||
| DGND
|
|
|-
|-
| P48
| P48 || FPGA/INIT_B || [JTAG]
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
|-
|-
| P49
| P49 || CP2201/AD0 || AD(0)
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
| Ethernet controller address/data bus, bit 0
|-
|-
| P50
| P50 || CP2201/AD1 || AD(1)
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
| Ethernet controller address/data bus, bit 1
|-
|-
| P51
| P51 || FPGA/DIN || [JTAG]
| FPGA/DIN
| Serial data input from EEPROM for configuration
| Serial data input from EEPROM for configuration
|-
|-
| P52
| P52 || CP2201/AD2 || AD(2)
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
| Ethernet controller address/data bus, bit 2
|-
|-
| P53
| P53 || FPGA/CCLK || [JTAG]
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
|-
|-
| P54
| P54 || FPGA/DONE || [JTAG]
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
| Gives configuration status - see Xilinx documentation
|-
|-
| P55
| P55 || +3.3V ||
| +3.3V
|
|
|-
|-
| P56
| P56 || CP2201/AD3 || AD(3)
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
| Ethernet controller address/data bus, bit 3
|-
|-
| P57
| P57 || CP2201/AD4 || AD(4)
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
| Ethernet controller address/data bus, bit 4
|-
|-
| P58
| P58 || DGND ||
| DGND
|
|
|-
|-
| P59
| P59 || CP2201/AD5 || AD(5)
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
| Ethernet controller address/data bus, bit 5
|-
|-
| P60
| P60 || CP2201/AD6 || AD(6)
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
| Ethernet controller address/date bus, bit 6
|-
|-
| P61
| P61 || CP2201/AD7 || AD(7)
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
| Ethernet controller address/date bus, bit 7
|-
|-
| P62
| P62 || No connection ||
| No connection
|
|
|-
|-
| P63
| P63 || DGND ||
| DGND
|
|
|-
|-
| P64
| P64 || No connection ||
| No connection
|
|
|-
|-
| P65
| P65 || No connection ||
| No connection
|
|
|-
|-
| P66
| P66 || +1.2V ||
| +1.2V
|
|
|-
|-
| P67
| P67 || +3.3V ||
| +3.3V
|
|
|-
|-
| P68
| P68 || +3.3V ||
| +3.3V
|
|
|-
|-
| P69
| P69 || DGND ||
| DGND
|
|
|-
|-
| P70
| P70 || ID3 || LocStamp(3)
| ID3
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
|-
|-
| P71
| P71 || ID2 || LocStamp(2)
| ID2
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
|-
|-
| P72
| P72 || ID1 || LocStamp(1)
| ID1
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
|-
|-
| P73
| P73 || ID0 || LocStamp(0)
| ID0
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
|-
|-
| P74
| P74 || DGND ||
| DGND
|
|
|-
|-
| P75
| P75 || FPGA/TDO || [JTAG]
| FPGA/TDO
| JTAG
| JTAG
|-
|-
| P76
| P76 || FPGA/TCK || [JTAG]
| FPGA/TCK
| JTAG
| JTAG
|-
|-
| P77
| P77 || ID4 || LocStamp(4)
| ID4
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
|-
|-
| P78
| P78 || No connection ||
| No connection
|
|
|-
|-
| P79
| P79 || +3.3V ||
| +3.3V
|
|
|-
|-
| P80
| P80 || DGND ||
| DGND
|
|
|-
|-
| P81
| P81 || +1.2V ||
| +1.2V
|
|
|-
|-
| P82
| P82 || No connection || (db) dbShort
| No connection
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
|
|-
|-
| P83
| P83 || CLK_5MHZ_2 || DAC_Clk
| CLK_5MHZ_2
| 5 MHz clock output for DAC
| 5 MHz clock output for DAC
|-
|-
| P84
| P84 || No connection ||
| No connection
|
|
|-
|-
| P85
| P85 || AD5535/DIN || DAC_serData
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
| DAC serial data input (FPGA out -> DAC in)
|-
|-
| P86
| P86 || No connection ||
| No connection
|
|-
| P87 || DGND ||
|
|
|-
|-
| P87
| P88 || AD5535/SYNC || DAC_setISync
| DGND
|
|
|-
|-
| P89
| P89 || No connection ||
| No connection
|
|
|-
|-
| P90
| P90 || No connection ||
| No connection
|
|
|-
|-
| P91
| P91 || DGND ||
| DGND
|
|
|-
|-
| P92
| P92 || +3.3V ||
| +3.3V
|
|
|-
|-
| P93
| P93 || AD7314/CE || SPI_TCE
| AD7314/CE
| Chip enable for temperature sensor
| Chip enable for temperature sensor
|-
|-
| P94
| P94 || No connection ||
| No connection
|
|
|-
|-
| P95
| P95 || DGND ||
| DGND
|
|
|-
|-
| P96
| P96 || +3.3V ||
| +3.3V
|
|
|-
|-
| P97
| P97 || SPI_SDI ||
| AD7928/DOUT
| '''Corrected
| '''Erroneously wired ADC SPI bus connection'''<br>Connects to DOUT on ADC
|-
|-
| P98
| P98 || AD5535/RESET || DAC_iRst
| AD5535/RESET
|Reset pin for DAC
| Reset pin for DAC
|-
|-
| P99
| P99 || DGND ||
| DGND
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
|
|-
|-
| P100
| P100 || FPGA/PROG_B || [JTAG]
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
|}
|}
| B1
| B1
| B3
| B3
|
| B6
|
| 6
|-
|-
| 1
| 1
| A2
| A2
| C4
| C4
|
| B7
|
| 7
|-
|-
| 2
| 2
| D1
| D1
| B2
| B2
|
| B4
|
| 4
|-
|-
| 3
| 3
| C2
| C2
| C3
| C3
|
| B5
|
| 5
|-
|-
| 4
| 4
| B3
| B3
| B4
| B4
|
| B8
|
| 8
|-
|-
| 5
| 5
| E2
| E2
| C2
| C2
|
| B3
|
| 3
|-
|-
| 6
| 6
| F3
| F3
| B1
| B1
|
| B2
|
| 2
|-
|-
| 7
| 7
| A4
| A4
| B5
| B5
|
| B10
|
| 10
|-
|-
| 8
| 8
| E4
| E4
| C5
| C5
|
| B9
|
| 9
|-
|-
| 9
| 9
| B5
| B5
| C6
| C6
|
| B11
|
| 11
|-
|-
| 10
| 10
| F5
| F5
| C1
| C1
|
| B1
|
| 1
|-
|-
| 11
| 11
| A6
| A6
| C7
| C7
|
| B13
|
| 13
|-
|-
| 12
| 12
| E6
| E6
| B6
| B6
|
| B12
|
| 12
|-
|-
| 13
| 13
| B7
| B7
| B7
| B7
|
| B14
|
| 14
|-
|-
| 14
| 14
| F7
| F7
| C10
| C10
|
| B19
|
| 19
|-
|-
| 15
| 15
| E8
| E8
| C8
| C8
|
| B15
|
| 15
|-
|-
| 16
| 16
| A8
| A8
| B8
| B8
|
| B16
|
| 16
|-
|-
| 17
| 17
| B9
| B9
| C9
| C9
|
| B17
|
| 17
|-
|-
| 18
| 18
| F9
| F9
| C16
| C16
|
| B31
|
| GAINMODE
|-
|-
| 19
| 19
| E10
| E10
| B11
| B11
|
| B22
|
| 22
|-
|-
| 20
| 20
| A10
| A10
| B9
| B9
|
| B18
|
| 18
|-
|-
| 21
| 21
| B11
| B11
| B10
| B10
|
| B20
|
| 20
|-
|-
| 22
| 22
| C12
| C12
| B12
| B12
|
| B24
|
| 24
|-
|-
| 23
| 23
| D13
| D13
| B13
| B13
|
| B26
|
| 26
|-
|-
| 24
| 24
| E12
| E12
| B14
| B14
|
| B28
|
| 28
|-
|-
| 25
| 25
| A12
| A12
| C11
| C11
|
| B21
|
| 21
|-
|-
| 26
| 26
| B13
| B13
| C12
| C12
|
| B23
|
| 23
|-
|-
| 27
| 27
| H13
| H13
| B16
| B16
|
| B30
|
| 30
|-
|-
| 28
| 28
| G14
| G14
| B15
| B15
|
| B27
|
| 27
|-
|-
| 29
| 29
| C14
| C14
| C13
| C13
|
| B25
|
| 25
|-
|-
| 30
| 30
| F13
| F13
| C15
| C15
|
| B29
|
| 29
|-
|-
| 31
| 31
| E14
| E14
| C14
| C14
|
| Not connected
| DACHEALTH<br>See [[#Channel Descriptions | ADC Channel Descriptions]].
| No amplifier connection<br>DACHEALTH<br>See [[#Channel Descriptions | ADC Channel Descriptions]].
|}
|}
| 15
| 15
| AD5535/CATHODE
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops -2.20mV/°C.
|-
|-
| VIN2
| VIN2
| 12
| 12
| ADC_EXT1
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
|-
| VIN5
| VIN5
| 10
| 10
| ADC_EXT2
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
|-
| VIN7
| VIN7