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Line 435: − + + − + + + + + + + + + + Line 610:
Line 523: − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + − + Line 809:
Line 722: − + + + + Line 831:
Line 747: − + Line 846:
Line 762: − + Line 856:
Line 772: − + − + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Digital control board documentation (view source)
Revision as of 20:22, 20 August 2010
, 20:22, 20 August 2010→Channel Descriptions
=== Pinout Table ===
=== Pinout Table ===
{| cellpadding=3 border=1 |
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Pin #''' || '''Net Name''' || '''Signal Name'''
| '''Net Name'''
| '''Description'''
| '''Description'''
|-
|-
| P1
| P1 || FPGA/TMS || [JTAG]
| FPGA/TMS
| JTAG
| JTAG
|-
|-
| P2
| P2 || FPGA/TDI || [JTAG]
| FPGA/TDI
| JTAG
| JTAG
|-
|-
| P3
| P3 || AD7928/CS || SPI_A_iCS
| AD7928/CS
| SPI chip select for ADC
| SPI chip select for ADC
|-
|-
| P4
| P4 || SPI || SPI_SDI
| SPI
| '''Corrected
| '''Erroneously wired SPI bus trace'''<br>Connects to SDO on temp. sensor and DIN on ADC
|-
|-
| P5
| P5 || CLK_5MHZ || SPI_SCLK
| CLK_5MHZ
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
|-
|-
| P6
| P6 || No connection ||
| No connection
|
|
|-
|-
| P7
| P7 || No connection ||
| No connection
|
|
|-
|-
| P8
| P8 || DGND ||
| DGND
|
|
|-
|-
| P9
| P9 || No connection ||
| No connection
|
|
|-
|-
| P10
| P10 || No connection ||
| No connection
|
|
|-
|-
| P11
| P11 || +3.3V ||
| +3.3V
|
|
|-
|-
| P12
| P12 || No connection ||
| No connection
|
|
|-
|-
| P13
| P13 || No connection ||
| No connection
|
|
|-
|-
| P14
| P14 || DGND ||
| DGND
|
|
|-
|-
| P15
| P15 || No connection ||
| No connection
|
|
|-
|-
| P16
| P16 || No connection ||
| No connection
|
|
|-
|-
| P17
| P17 || +1.2V ||
| +1.2V
|
|
|-
|-
| P18
| P18 || DGND ||
| DGND
|
|
|-
|-
| P19
| P19 || dBinfo_Start ||
| No connection
|
|
|-
|-
| P20
| P20 || dBinfo_Stream ||
| No connection
|
|
|-
|-
| P21
| P21 || No connection ||
| No connection
|
|
|-
|-
| P22
| P22 || +3.3V ||
| +3.3V
|
|
|-
|-
| P23
| P23 || DGND || [M1: JTAG prog. config.]
| DGND
|
|
|-
|-
| P24
| P24 || DGND || [M2: JTAG prog. config.]
| DGND
|
|
|-
|-
| P25
| P25 || DGND || [M0: JTAG prog. config.]
| DGND
|
|
|-
|-
| P26
| P26 || +3.3V ||
| +3.3V
|
|
|-
|-
| P27
| P27 || FPGA/CLK_IN || fClk
| FPGA/CLK_IN
| 20 MHz clock input from crystal oscillator
| 20 MHz clock input from crystal oscillator
|-
|-
| P28
| P28 || No connection ||
| No connection
|
|
|-
|-
| P29
| P29 || No connection || (db) state_Q(0)
| No connection
|
|
|-
|-
| P30
| P30 || No connection ||
| No connection
|
|
|-
|-
| P31
| P31 || No connection || (db) state_Q(1)
| No connection
|
|
|-
|-
| P32
| P32 || No connection ||
| No connection
|
|
|-
|-
| P33
| P33 || No connection || (db) state_Q(2)
| No connection
|
|
|-
|-
| P34
| P34 || No connection ||
| No connection
|
|
|-
|-
| P35
| P35 || CP2201/INT || Eth_iINT
| CP2201/INT
| Ethernet controller interrupt
| Ethernet controller interrupt
|-
|-
| P36
| P36 || MASTER_RESET || Rst
| MASTER_RESET
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
|-
|-
| P37
| P37 || (manually wired) || fClk_out
| No connection
|
|
|-
|-
| P38
| P38 || +1.2V ||
| +1.2V
|
|
|-
|-
| P39
| P39 || No connection ||
| No connection
|
|
|-
|-
| P40
| P40 || CP2201/CS || iCS
| CP2201/CS
| Chip select for ethernet controller
| Chip select for ethernet controller
|-
|-
| P41
| P41 || CP2201/WR || iWR
| CP2201/WR
| Write enable for ethernet controller
| Write enable for ethernet controller
|-
|-
| P42
| P42 || DGND ||
| DGND
|
|
|-
|-
| P43
| P43 || CP2201/RD || iRD
| CP2201/RD
| Read enable for ethernet controller
| Read enable for ethernet controller
|-
|-
| P44
| P44 || CP2201/ALE || ALE
| CP2201/ALE
| Address line enable for ethernet controller
| Address line enable for ethernet controller
|-
|-
| P45
| P45 || +3.3V ||
| +3.3V
|
|
|-
|-
| P46
| P46 || CP2201/RESET || Eth_iRst
| CP2201/RESET
| Reset pin for ethernet controller
| Reset pin for ethernet controller
|-
|-
| P47
| P47 || DGND ||
| DGND
|
|
|-
|-
| P48
| P48 || FPGA/INIT_B || [JTAG]
| FPGA/INIT_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
|-
|-
| P49
| P49 || CP2201/AD0 || AD(0)
| CP2201/AD0
| Ethernet controller address/data bus, bit 0
| Ethernet controller address/data bus, bit 0
|-
|-
| P50
| P50 || CP2201/AD1 || AD(1)
| CP2201/AD1
| Ethernet controller address/data bus, bit 1
| Ethernet controller address/data bus, bit 1
|-
|-
| P51
| P51 || FPGA/DIN || [JTAG]
| FPGA/DIN
| Serial data input from EEPROM for configuration
| Serial data input from EEPROM for configuration
|-
|-
| P52
| P52 || CP2201/AD2 || AD(2)
| CP2201/AD2
| Ethernet controller address/data bus, bit 2
| Ethernet controller address/data bus, bit 2
|-
|-
| P53
| P53 || FPGA/CCLK || [JTAG]
| FPGA/CCLK
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
| Configuration clock (signal generated by FPGA at <br>power on to clock the configuration process)<br>See Xilinx documentation
|-
|-
| P54
| P54 || FPGA/DONE || [JTAG]
| FPGA/DONE
| Gives configuration status - see Xilinx documentation
| Gives configuration status - see Xilinx documentation
|-
|-
| P55
| P55 || +3.3V ||
| +3.3V
|
|
|-
|-
| P56
| P56 || CP2201/AD3 || AD(3)
| CP2201/AD3
| Ethernet controller address/data bus, bit 3
| Ethernet controller address/data bus, bit 3
|-
|-
| P57
| P57 || CP2201/AD4 || AD(4)
| CP2201/AD4
| Ethernet controller address/data bus, bit 4
| Ethernet controller address/data bus, bit 4
|-
|-
| P58
| P58 || DGND ||
| DGND
|
|
|-
|-
| P59
| P59 || CP2201/AD5 || AD(5)
| CP2201/AD5
| Ethernet controller address/data bus, bit 5
| Ethernet controller address/data bus, bit 5
|-
|-
| P60
| P60 || CP2201/AD6 || AD(6)
| CP2201/AD6
| Ethernet controller address/date bus, bit 6
| Ethernet controller address/date bus, bit 6
|-
|-
| P61
| P61 || CP2201/AD7 || AD(7)
| CP2201/AD7
| Ethernet controller address/date bus, bit 7
| Ethernet controller address/date bus, bit 7
|-
|-
| P62
| P62 || No connection ||
| No connection
|
|
|-
|-
| P63
| P63 || DGND ||
| DGND
|
|
|-
|-
| P64
| P64 || No connection ||
| No connection
|
|
|-
|-
| P65
| P65 || No connection ||
| No connection
|
|
|-
|-
| P66
| P66 || +1.2V ||
| +1.2V
|
|
|-
|-
| P67
| P67 || +3.3V ||
| +3.3V
|
|
|-
|-
| P68
| P68 || +3.3V ||
| +3.3V
|
|
|-
|-
| P69
| P69 || DGND ||
| DGND
|
|
|-
|-
| P70
| P70 || ID3 || LocStamp(3)
| ID3
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 3 & 4<br>Active-low, FPGA should pull high
|-
|-
| P71
| P71 || ID2 || LocStamp(2)
| ID2
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 5 & 6<br>Active-low, FPGA should pull high
|-
|-
| P72
| P72 || ID1 || LocStamp(1)
| ID1
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 7 & 8<br>Active-low, FPGA should pull high
|-
|-
| P73
| P73 || ID0 || LocStamp(0)
| ID0
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 9 & 10<br>Active-low, FPGA should pull high
|-
|-
| P74
| P74 || DGND ||
| DGND
|
|
|-
|-
| P75
| P75 || FPGA/TDO || [JTAG]
| FPGA/TDO
| JTAG
| JTAG
|-
|-
| P76
| P76 || FPGA/TCK || [JTAG]
| FPGA/TCK
| JTAG
| JTAG
|-
|-
| P77
| P77 || ID4 || LocStamp(4)
| ID4
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
| Backplane location identifier jumper, pins 1 & 2<br>Active-low, FPGA should pull high
|-
|-
| P78
| P78 || No connection ||
| No connection
|
|
|-
|-
| P79
| P79 || +3.3V ||
| +3.3V
|
|
|-
|-
| P80
| P80 || DGND ||
| DGND
|
|
|-
|-
| P81
| P81 || +1.2V ||
| +1.2V
|
|
|-
|-
| P82
| P82 || No connection || (db) dbShort
| No connection
| Shorts out the waiting timer in FPGA for Ethernet controller initialization (pulled low)
|
|-
|-
| P83
| P83 || CLK_5MHZ_2 || DAC_Clk
| CLK_5MHZ_2
| 5 MHz clock output for DAC
| 5 MHz clock output for DAC
|-
|-
| P84
| P84 || No connection ||
| No connection
|
|
|-
|-
| P85
| P85 || AD5535/DIN || DAC_serData
| AD5535/DIN
| DAC serial data input (FPGA out -> DAC in)
| DAC serial data input (FPGA out -> DAC in)
|-
|-
| P86
| P86 || No connection ||
| No connection
|
|-
| P87 || DGND ||
|
|
|-
|-
| P87
| P88 || AD5535/SYNC || DAC_setISync
| DGND
|
|
|-
|-
| P89
| P89 || No connection ||
| No connection
|
|
|-
|-
| P90
| P90 || No connection ||
| No connection
|
|
|-
|-
| P91
| P91 || DGND ||
| DGND
|
|
|-
|-
| P92
| P92 || +3.3V ||
| +3.3V
|
|
|-
|-
| P93
| P93 || AD7314/CE || SPI_TCE
| AD7314/CE
| Chip enable for temperature sensor
| Chip enable for temperature sensor
|-
|-
| P94
| P94 || No connection ||
| No connection
|
|
|-
|-
| P95
| P95 || DGND ||
| DGND
|
|
|-
|-
| P96
| P96 || +3.3V ||
| +3.3V
|
|
|-
|-
| P97
| P97 || SPI_SDI ||
| AD7928/DOUT
| '''Corrected
| '''Erroneously wired ADC SPI bus connection'''<br>Connects to DOUT on ADC
|-
|-
| P98
| P98 || AD5535/RESET || DAC_iRst
| AD5535/RESET
|Reset pin for DAC
| Reset pin for DAC
|-
|-
| P99
| P99 || DGND ||
| DGND
| PUDC_B pin - enables pullup resistors on user IO and input-only pins during FPGA config.
|
|-
|-
| P100
| P100 || FPGA/PROG_B || [JTAG]
| FPGA/PROG_B
| Used during FPGA configuration - see Xilinx documentation
| Used during FPGA configuration - see Xilinx documentation
|}
|}
===Pinout Table===
===Pinout Table===
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. '''Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.'''
Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Improper wiring will certainly cause undesired operation, and may cause damage as well. Damage is most likely to occur if one of the flying leads is improperly connected to an odd numbered pin, since it will short to the PCB's ground plane.
{| cellpadding=3 border=1 |
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Pin #'''
| '''Net Name'''
| '''Net Name'''
| '''Flying Lead'''
| '''Description'''
| '''Description'''
|-
|-
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| 1, 3, 5, 7, 9, 11, 13 (odd pins)
| DGND
| DGND
| Ground pins for signal integrity<br>'''Never connect a flying lead to these pins'''<br>Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
| Black (connect to any odd numbered pin)
| Ground pins for signal integrity<br>'''Never connect a flying lead other than the black lead to an odd numbered pin'''<br>Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
|-
|-
| 2
| 2
| +3.3V
| +3.3V
| <span style="color: red">Red/VREF</span>
| Power source for all JTAG logic
| Power source for all JTAG logic
|-
|-
| 4
| 4
| FPGA/TMS
| FPGA/TMS
| <span style="color: green">Green/TMS</span>
| JTAG TMS - connects to EEPROM and FPGA
| JTAG TMS - connects to EEPROM and FPGA
|-
|-
| 6
| 6
| FPGA/TCK
| FPGA/TCK
| <span style="color: yellow">Yellow/TCK</span>
| JTAG TCK - connects to EEPROM and FPGA
| JTAG TCK - connects to EEPROM and FPGA
|-
|-
| 8
| 8
| FPGA/TDO
| FPGA/TDO
| <span style="color: purple">Purple/TDO</span>
| JTAG boundary scan chain endpoint
| JTAG boundary scan chain endpoint
|-
|-
| 10
| 10
| EEPROM/TDI
| EEPROM/TDI
| White/TDI
| JTAG boundary scan chain start point
| JTAG boundary scan chain start point
|-
|-
| 12
| 12
| No connection
| No connection
|
| Pin is floating
| Pin is floating
|-
|-
| 14
| 14
| No connection
| No connection
|
| Pin is floating
| Pin is floating
|}
|}
''The gray HALT flying lead is not connected.''
===JTAG Overview===
===JTAG Overview===
| '''Digital Board Eurocard Pin #'''
| '''Digital Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Amplifier Board Eurocard Pin #'''
| '''Physical Channel #'''
| '''Amplifier Channel #'''
|-
|-
| 0
| 0
| B1
| B1
| B3
| B3
|
| B6
|
| 6
|-
|-
| 1
| 1
| A2
| A2
| C4
| C4
|
| B7
|
| 7
|-
|-
| 2
| 2
| D1
| D1
| B2
| B2
|
| B4
|
| 4
|-
|-
| 3
| 3
| C2
| C2
| C3
| C3
|
| B5
|
| 5
|-
|-
| 4
| 4
| B3
| B3
| B4
| B4
|
| B8
|
| 8
|-
|-
| 5
| 5
| E2
| E2
| C2
| C2
|
| B3
|
| 3
|-
|-
| 6
| 6
| F3
| F3
| B1
| B1
|
| B2
|
| 2
|-
|-
| 7
| 7
| A4
| A4
| B5
| B5
|
| B10
|
| 10
|-
|-
| 8
| 8
| E4
| E4
| C5
| C5
|
| B9
|
| 9
|-
|-
| 9
| 9
| B5
| B5
| C6
| C6
|
| B11
|
| 11
|-
|-
| 10
| 10
| F5
| F5
| C1
| C1
|
| B1
|
| 1
|-
|-
| 11
| 11
| A6
| A6
| C7
| C7
|
| B13
|
| 13
|-
|-
| 12
| 12
| E6
| E6
| B6
| B6
|
| B12
|
| 12
|-
|-
| 13
| 13
| B7
| B7
| B7
| B7
|
| B14
|
| 14
|-
|-
| 14
| 14
| F7
| F7
| C10
| C10
|
| B19
|
| 19
|-
|-
| 15
| 15
| E8
| E8
| C8
| C8
|
| B15
|
| 15
|-
|-
| 16
| 16
| A8
| A8
| B8
| B8
|
| B16
|
| 16
|-
|-
| 17
| 17
| B9
| B9
| C9
| C9
|
| B17
|
| 17
|-
|-
| 18
| 18
| F9
| F9
| C16
| C16
|
| B31
|
| GAINMODE
|-
|-
| 19
| 19
| E10
| E10
| B11
| B11
|
| B22
|
| 22
|-
|-
| 20
| 20
| A10
| A10
| B9
| B9
|
| B18
|
| 18
|-
|-
| 21
| 21
| B11
| B11
| B10
| B10
|
| B20
|
| 20
|-
|-
| 22
| 22
| C12
| C12
| B12
| B12
|
| B24
|
| 24
|-
|-
| 23
| 23
| D13
| D13
| B13
| B13
|
| B26
|
| 26
|-
|-
| 24
| 24
| E12
| E12
| B14
| B14
|
| B28
|
| 28
|-
|-
| 25
| 25
| A12
| A12
| C11
| C11
|
| B21
|
| 21
|-
|-
| 26
| 26
| B13
| B13
| C12
| C12
|
| B23
|
| 23
|-
|-
| 27
| 27
| H13
| H13
| B16
| B16
|
| B30
|
| 30
|-
|-
| 28
| 28
| G14
| G14
| B15
| B15
|
| B27
|
| 27
|-
|-
| 29
| 29
| C14
| C14
| C13
| C13
|
| B25
|
| 25
|-
|-
| 30
| 30
| F13
| F13
| C15
| C15
|
| B29
|
| 29
|-
|-
| 31
| 31
| E14
| E14
| C14
| C14
|
| Not connected
| DACHEALTH... anything else??
| No amplifier connection<br>DACHEALTH<br>See [[#Channel Descriptions | ADC Channel Descriptions]].
|}
|}
===Power Details===
===Power Details===
The ADC is powered by the +5V power island, regulated by an off-board power supply, and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.
The ADC is powered by the +5V power island, which is regulated by an off-board power supply and decoupled near the ADC. It also requires a precise (±1%) 2.5V reference to which it compares voltages when converting from analog to digital. Since the +5V power source is not used for comparison, it is flexible and may vary by ±0.25V without affecting ADC precision.
===Setting the Measuring Range===
===Setting the Measuring Range===
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).
The measuring range is set programmatically by the FPGA over the SPI bus. The way the ADC is connected on the digital board requires that its measuring range be set to 5V, so the RANGE bit should be set to 1 by the FPGA (see Analog Devices documentation).
===Data Interfacing===
The ADC uses an SPI bus to communicate with the FPGA. This bus is shared with the temperature sensor. SPI related pins include SCLK, CS, DIN, and DOUT. See the Pinout Table below.
===Channel Descriptions===
===Channel Descriptions===
| 15
| 15
| AD5535/CATHODE
| AD5535/CATHODE
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops 2.20mV/°C.
| This is the thermal diode output from the DAC. Should read 4.35V (typical) at 25°C. Drops -2.20mV/°C.
|-
|-
| VIN2
| VIN2
| 12
| 12
| ADC_EXT1
| ADC_EXT1
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
|-
|-
| VIN5
| VIN5
| 10
| 10
| ADC_EXT2
| ADC_EXT2
| This trace routes to the backplane via Eurocard pin A8. It is intended to measure one of the transistor base voltages on the amplifier board.
| This trace routes to the backplane via Eurocard pin A7. It is intended to measure the output of thermistor on the amplifier board.
|-
|-
| VIN7
| VIN7
| 9
| 9
| DACHEALTH
| DACHEALTH
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.878V. Since the divider should be linear, the expected voltage at 20V is 0.4878V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current. The channel is routed to the backplane nonetheless.
| This channel monitors the output of a resistor divider connected to channel 31 of the DAC. The divider consists of three resistors of 200K, 200K, and 10.2K (in order). The ADC reads out the voltage level between the second 200K and then 10.2K resistor. These resistors were selected so that at 200V, the readout voltage will be 4.973V. Since the divider should be linear, the expected voltage at 20V is 0.4973V. Three resistors were used rather than two to avoid exceeding the resistors' power ratings when the DAC is set to its maximum voltage. Note that since this divider will consume up to 484uA of current at 200V, this DAC channel should not be used for anything that might require more than ~200uA of current (the DAC can source 700uA max). The channel is routed to the backplane nonetheless.
|}
===Pinout Table===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CLK_5MHZ
| SPI clock (SCLK), from FPGA<br>Shared with temperature sensor
|-
| 2
| DIN
| SPI data in, from FPGA<br>Shared with temperature sensor<br>''Currently wired wrong''
|-
| 3
| CS
| SPI chip select
|-
| 4
| AGND
|
|-
| 5
| +5V
| Power pin
|-
| 6
| +5V
| Power pin
|-
| 7
| AD7928/REF_IN
| +2.5V reference, set by VR2
|-
| 8
| AGND
|
|-
| 9-16
| VIN[7:0]
| See [[#Channel Descriptions | ADC Channel Descriptions]]
|-
| 17
| AGND
|
|-
| 18
| DOUT
| SPI data out<br>''Currently wired incorrectly''
|-
| 19
| +3.3V
| VDRIVE, powers the SPI logic
|-
| 20
| AGND
|
|}
== Ethernet Controller ==
The board uses a Silicon Laboratories CP2201, 28-pin, ethernet controller. The CP2201 is located just above the FPGA, and is labelled U2.
=== Power Details ===
The CP2201 uses only +3.3V, which is supplied by the +3.3V power plane and regulated by VR1. Appropriate decoupling capacitors can be found near the CP2201.
=== Ethernet Jack ===
To the right of the CP2201 is a Pulse J0011D21NL ethernet jack, labelled J1. This jack has a built-in 1:1 inductive coupling. For best results, connect this jack to a nearby ethernet switch. The jack may also be connected directly to a computer using a crossover cable. Though auto-crossover is not supported by the CP2201, if the computer's NIC supports it, a crossover cable is not necessary to connect directly to a computer.
==== Ethernet Jack Pins ====
These are visible only on the back side of the board. Pin 1 is indicated by a square pad. Pin 8 is the farthest pin from pin 1. Pins are numbered such that the 4 pins closer to the plastic thru-hole connectors are odd (1, 3, 5, 7), and the four pins closer to the CP2201 are are even (2, 4, 6, 8).
* Pin 1: TX+
* Pin 2: AC coupled to DGND
* Pin 3: TX-
* Pin 4: RX+
* Pin 5: AC coupled to DGND
* Pin 6: RX-
* Pin 7: No connection
* Pin 8: DGND (direct)
The two large thru-hole pins (not numbered) connect to the metal shielding on the outside of the jack. These are directly connected to DGND to shield against electrical noise inside the jack.
The two plastic thru-hole pins are not conductive and have no electrical connection. They are present only for structural purposes, presumably to prevent stress on the solder points when an ethernet wire is inserted or removed from the jack.
=== Crystal Oscillator ===
The CP2201 is responsible for driving the 20MHz crystal oscillator. This oscillator clocks both the CP2201 and the FPGA. The crystal oscillator can be found above the right corner of the FPGA. It can be identified by its four surface mount pads and roughly .3" length. It is labelled Y1, though this label is not visible after the oscillator is soldered on. The CP2201 uses an inverting driver to excite the crystal. The output of the crystal is then sent to the CP2201 and the FPGA.
=== Bus Format and Multiplexing ===
The 28-pin CP2201 used on the board only supports multiplexed operation. This means that both address and data information are passed over the same set of 8 traces. Hence, these traces are referred to as the address/data (AD) bus. A separate address line enable (ALE) trace prevents collisions from occuring on these traces. The communication protocol used is the Intel format. See the CP2201's datasheet for more information about this.
=== Pinout Table ===
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| 1
| CP2201/LA
| Link/activity indicator<br>Routed to backplane but not implemented<br>See CP2201 data sheet for information on how to connect to an LED
|-
| 2
| DGND
| By the data sheet, this pin should be AGND<br>We deliberately set it to DGND to avoid noise on AGND plane
|-
| 3
| +3.3V
| AV+ power pin
|-
| 4
| CP2201/RX-
| Connects to RX- on ethernet jack
|-
| 5
| CP2201/RX+
| Connects to RX+ on ethernet jack
|-
| 6
| CP2201/TX+
| Connects to TX+ on ethernet jack
|-
| 7
| CP2201/TX-
| Connects to TX- on ethernet jack
|-
| 8
| +3.3V
| "VDD" power pin
|-
| 9
| DGND
| "DGND1" per the data sheet
|-
| 10
| CP2201/RESET
| "RST" per the data sheet<br>Connects to FPGA - should be programmatically triggered upon reset of FPGA by RESET jumper
|-
| 11-18
| CP2201/AD[0:7]
| Bits 0-7 of the address/data bus<br>Connect to FPGA
|-
| 19
| +3.3V
| "VDD" power pin
|-
| 20
| DGND
| "DGND2" per the data sheet
|-
| 21
| CP2201/ALE
| Address line enable<br>Connects to FPGA<br>See CP2201 documentation
|-
| 22
| CP2201/RD
| Read strobe for AD bus<br>Connects to FPGA<br>See CP2201 documentation
|-
| 23
| CP2201/WR
| Write strobe for AD bus<br>Connects to FPGA<br>See CP2201 documentation
|-
| 24
| CP2201/CS
| Chip select<br>Connects to FPGA
|-
| 25
| CP2201/INT
| Interrupt request<br>Connects to FPGA
|-
| 26
| DGND
| "MOTEN" (Motorola enable) per the datasheet<br>Tied low to disable Motorola bus format (enable Intel format)
|-
| 27
| CP2201/XTAL2
| Crystal oscillator driver<br>The CP2201 inverts the 20MHz clock signal and feeds it back to the crystal oscillator to encourage larger oscillations
|-
| 28
| FPGA/CLK_IN
| "XTAL1" per the data sheet<br>This is the 20MHz clock input<br>Also connects to the FPGA's clock input
|-
| 29*
| DGND
| This is not a pin but rather the base of the CP2201 package.<br>It is connected to the DGND plane for thermal relief
|}
== Eurocard Connector ==
At the bottom of the control board is the Eurocard connector, labelled P2. The Eurocard connector connects the board to the backplane and also connects the board to its power supplies. The Eurocard has 48 pins arranged in three rows of 16 pins each. Rows B and C are exclusively used to pass SiPM bias voltages to the backplane as described in [[#Channel Mapping | DAC Channel Mapping]]. Here is a table describing the purpose of pins in row A:
=== Row A Pinout Table ===
Note that when viewing the front side of the board with the Eurocard at the bottom, these pins go from right to left. If you look closely at the pins, you will see that pin A1 has a square pad, unlike the round pads of the others.
{| cellpadding=3 border=1 |
| '''Pin #'''
| '''Net Name'''
| '''Description'''
|-
| A1
| CP2201/LA
| Ethernet link/activity indicator routed to backplane
|-
| A2
| High voltage input (+210V max)
| High voltage input for DAC. See [[#DAC | DAC]] for information about what voltage to input here.
|-
| A3
| -5V
| For DAC
|-
| A4
| +5V
| Powers most things on the board
|-
| A5
| AGND
|
|-
| A6
| DGND
|
|-
| A7
| ADC_EXT1
| Connects to ADC to monitor voltages on amplifier board<br>See [[#ADC | ADC]]
|-
| A8
| ADC_EXT2
| Connects to ADC to monitor voltages on amplifier board<br>See [[#ADC | ADC]]
|-
| A9
| No connection
|
|-
| A10
| No connection
|
|-
| A11
| No conneciton
|
|-
| A12
| ID4
| Location identifier bit 4<br>Used to identify which backplane board is connected to<br>See [[#FPGA | FPGA]]
|-
| A13
| ID3
| Location identifier bit 3<br>Used to identify which backplane board is connected to<br>See [[#FPGA | FPGA]]
|-
| A14
| ID2
| Location identifier bit 2<br>Used to identify which backplane board is connected to<br>See [[#FPGA | FPGA]]
|-
| A15
| ID1
| Location identifier bit 1<br>Used to identify which backplane board is connected to<br>See [[#FPGA | FPGA]]
|-
| A16
| ID0
| Location identifier bit 0<br>Used to identify which backplane board is connected to<br>See [[#FPGA | FPGA]]
|}
|}