Difference between revisions of "FPGA Transmitter"
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The Transmitter is responsible for compiling report packets for sending to the PC. As discussed [[Ethernet packets#"S" packet: status report|elsewhere]], the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the [[FPGA_Idler|Idler]] to await the next request from the PC. | The Transmitter is responsible for compiling report packets for sending to the PC. As discussed [[Ethernet packets#"S" packet: status report|elsewhere]], the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the [[FPGA_Idler|Idler]] to await the next request from the PC. | ||
| + | Since the time required to compose a packet by this module is about the same as the time to receive a minimum-length packet, the Transmitter temporarily disables the EC's Receiver Interface. | ||
| − | == Programming Details | + | |
| + | == Programming Details == | ||
The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1. | The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, ''DPAcket'' and ''SPacket'' with a "Go" signal selected by the state bit 1. | ||
The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the ''RAwrToAddr'' (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored. | The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the ''RAwrToAddr'' (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored. | ||
| + | |||
| + | The child S/D modules are passed the relevant subset of Transmitter's external buses. They essentially count through the addresses of the appropriate data registers and pass the data into the transmit buffer of the EC in 2-byte words. As elsewhere transmissions of this type are done by ''RAwr2BtoAddr'' module which latches the 2-byte input and uses ''RAwrToAddr'' to write the two sequential bytes using the random-access method. | ||
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* ''Clk'': [in] clock | * ''Clk'': [in] clock | ||
| + | * ''Rst: [in] asynchronous reset | ||
| − | + | [[FPGA_Registers#State_Register|State Register]] Control Lines | |
| − | * '' | + | * ''state_En'': [out] state register enable (write) signal |
| + | * ''state_D'': [out] (3-bit) state register input | ||
| + | * ''state_Q'': [in] (3-bit) state register output | ||
| + | |||
| + | * ''LocStamp'': [in] 8-bit board location value as hard-coded into the board's slot | ||
| − | + | [[FPGA_Registers#MAC_Register|MAC Address Register]] Control Lines | |
| + | * ''MACregs_A'': [out] byte address (4-bit) | ||
| + | * ''MACregs_Q'': [in] 8-bit value | ||
| − | |||
| − | + | [[FPGA_Registers#Temperature Register|Temperature]], [[FPGA_Registers#ADC Registers|ADC]] and [[FPGA_Registers#DAC Registers|DAC]] register control lines | |
| − | * '' | + | * ''TempReg_Q'': [in] 16-bit (pre-padded 10-bit) Temperature register value |
| − | * '' | + | * ''ADCReg_Addr'': [out] 3-bit ADC register address |
| − | * '' | + | * ''ADCReg_Q'': [in] 16-bit (pre-padded 12-bit) ADC register value |
| + | * ''DACReg_Addr'': [out] 5-bit DAC register address bus | ||
| + | * ''DACReg_Q'': [in] 16-bit (pre-padded 14-bit) DAC register value | ||
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| − | + | [[FPGA_Transceiver|Transceiver]] Control Lines | |
| − | + | * ''TxRx_Go'': [out] "Go" signal to read/write an EC control register byte | |
| − | + | * ''TxRx_RiW'': [out] active-high read, active-low write flag | |
| − | + | * ''TxRx_Aout'': [out] EC control register address (8-bit) | |
| − | + | * ''TxRx_Dout'': [out] EC control register write value | |
| − | + | * ''TxRx_Done'': [in] "Done" signal from [[FPGA_Transceiver|Transceiver]] | |
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Latest revision as of 06:31, 5 November 2009
(1X1) Transmitter
The Transmitter is responsible for compiling report packets for sending to the PC. As discussed elsewhere, the output packets from the digital boards come in "S" and "D" varieties corresponding to "status" - data from sensor chips, and "DAC values" respectively. The selection between these packet types is articulated via the middle bit of the state value: 101 corresponds to S-packet and 111 corresponds to D-packet. After composing the packet and ordering its transmission via the interface with the Ethernet Controller chip (EC), the module yields control to the Idler to await the next request from the PC.
Since the time required to compose a packet by this module is about the same as the time to receive a minimum-length packet, the Transmitter temporarily disables the EC's Receiver Interface.
Programming Details
The natural design approach for this dual-purpose block (sending two very different packets) is to perform the general preparations for transmission including the transmissions buffer pointer settings and packet header composition and then pass control to one of the two child modules that append the appropriate data to the packet depending on the packet type. As such, the Transmitter is enabled when the state value bits 2 and 0 are high and in due course pulses its child modules, DPAcket and SPacket with a "Go" signal selected by the state bit 1.
The major complication in our approach to packet composition is the limited auto-write (easy sequential write) interface of the transmission buffer of the CP220X chips. Upon a transmission failure the auto-write interface is disabled, forcing the controller to switch to random access mode. We resolved, in our design, to just use the latter approach. This mode requires setting the 16-bit buffer address pointer and then writing the desired 8-bit value. Thus, every byte required three write operations. These operations have been aggregated into the RAwrToAddr (Random Access WRite TO ADDRess) module to abstract this complication from the higher-level Transmitter block. One feature of this modules is that it remembers the address of the last byte written and can be told to advance by itself to the next address by writing '1' to the MSB of its address bus. The caveat to using this feature is that the module must only be instantiated once and its control lines must be passed to the children. In this way, the simplicity of the auto-write interface is, in some sense, restored.
The child S/D modules are passed the relevant subset of Transmitter's external buses. They essentially count through the addresses of the appropriate data registers and pass the data into the transmit buffer of the EC in 2-byte words. As elsewhere transmissions of this type are done by RAwr2BtoAddr module which latches the 2-byte input and uses RAwrToAddr to write the two sequential bytes using the random-access method.
Ports
- Clk: [in] clock
- Rst: [in] asynchronous reset
State Register Control Lines
- state_En: [out] state register enable (write) signal
- state_D: [out] (3-bit) state register input
- state_Q: [in] (3-bit) state register output
- LocStamp: [in] 8-bit board location value as hard-coded into the board's slot
MAC Address Register Control Lines
- MACregs_A: [out] byte address (4-bit)
- MACregs_Q: [in] 8-bit value
Temperature, ADC and DAC register control lines
- TempReg_Q: [in] 16-bit (pre-padded 10-bit) Temperature register value
- ADCReg_Addr: [out] 3-bit ADC register address
- ADCReg_Q: [in] 16-bit (pre-padded 12-bit) ADC register value
- DACReg_Addr: [out] 5-bit DAC register address bus
- DACReg_Q: [in] 16-bit (pre-padded 14-bit) DAC register value
Transceiver Control Lines
- TxRx_Go: [out] "Go" signal to read/write an EC control register byte
- TxRx_RiW: [out] active-high read, active-low write flag
- TxRx_Aout: [out] EC control register address (8-bit)
- TxRx_Dout: [out] EC control register write value
- TxRx_Done: [in] "Done" signal from Transceiver