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Line 1: − The VHDL files can be found [http://zeus.phys.uconn.edu/halld/tagger/electronics/design-6-2007/ADC_VHDL.zip here]. − Line 39:
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== Interface ==
== Interface ==
** if 1, analog input range is 0 to V<sub>Reg</sub>
** if 1, analog input range is 0 to V<sub>Reg</sub>
* Coding: set to zero
* Coding: set to zero
** if 0, output is twos-complement
** if 0, output is two's complement [http://en.wikipedia.org/wiki/Two%27s_complement]
** if 1, output is binary-coded decimal
** if 1, output is binary-coded decimal (BCD)
Thus a conversation to read the voltage only (and not update the control register would look like
Thus a conversation to read the voltage only (and not update the control register would look like
where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved. The don't-care states in bits 9 and 2 we can set to zero.
where an X is a don't-care state. Since the first case is almost all don't-care states, we can send the same data (last 11 bits) as in the second case, but append a zero to the front instead of a 1; this simplifies the logic involved. The don't-care states in bits 9 and 2 we can set to zero.
The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation. We are going to use twos-complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.
The data flowing back to the FPGA from the ADC will be voltage data from the channel set in the previous conversation. We are going to use two's complement format for the data, but it can be set to BCD by changing the last bit in the control register to a one.
The control interface to the FPGA core will be:
The control interface to the FPGA core will be: