Digital control board documentation

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

Power Requirements

Required Voltages

All components on the digital board except the DAC can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage (see Setting the Output Range). Digital and analog grounds must be connected as well before any testing takes place.

Power Pins

Power shall be connected to the board as follows:

Voltage	Eurocard Pin
DGND	A6
AGND	A5
+5V	A4
-5V	A3
High voltage (DAC max out +10)	A2

Power Supply Sequencing

The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

1. Ensure AGND/DGND are connected/grounded
2. +5V
3. -5V
4. High voltage

FPGA

The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

Power Details

The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

Logic Standard

The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a 3.3V CMOS logic standard.

Pinout Table

Pin #	Net Name	Description
P1	FPGA/TMS	JTAG
P2	FPGA/TDI	JTAG
P3	AD7928/CS	SPI chip select for ADC
P4	SPI	Erroneously wired SPI bus trace Connects to SDO on temp. sensor and DIN on ADC
P5	CLK_5MHZ	5 MHz clock output for SPI bus (ADC and temp. sensor)
P6	No connection
P7	No connection
P8	DGND
P9	No connection
P10	No connection
P11	+3.3V
P12	No connection
P13	No connection
P14	DGND
P15	No connection
P16	No connection
P17	+1.2V
P18	DGND
P19	No connection
P20	No connection
P21	No connection
P22	+3.3V
P23	DGND
P24	DGND
P25	DGND
P26	+3.3V
P27	FPGA/CLK_IN	20 MHz clock input from crystal oscillator
P28	No connection
P29	No connection
P30	No connection
P31	No connection
P32	No connection
P33	No connection
P34	No connection
P35	CP2201/INT	Ethernet controller interrupt
P36	MASTER_RESET	Connects to RESET jumper in upper left of board (active-low, externally pulled up)
P37	No connection
P38	+1.2V
P39	No connection
P40	CP2201/CS	Chip select for ethernet controller
P41	CP2201/WR	Write enable for ethernet controller
P42	DGND
P43	CP2201/RD	Read enable for ethernet controller
P44	CP2201/ALE	Address line enable for ethernet controller
P45	+3.3V
P46	CP2201/RESET	Reset pin for ethernet controller
P47	DGND
P48	FPGA/INIT_B	Used during FPGA configuration - see Xilinx documentation
P49	CP2201/AD0	Ethernet controller address/data bus, bit 0
P50	CP2201/AD1	Ethernet controller address/data bus, bit 1
P51	FPGA/DIN	Serial data input from EEPROM for configuration
P52	CP2201/AD2	Ethernet controller address/data bus, bit 2
P53	FPGA/CCLK	Configuration clock (signal generated by FPGA at power on to clock the configuration process) See Xilinx documentation
P54	FPGA/DONE	Gives configuration status - see Xilinx documentation
P55	+3.3V
P56	CP2201/AD3	Ethernet controller address/data bus, bit 3
P57	CP2201/AD4	Ethernet controller address/data bus, bit 4
P58	DGND
P59	CP2201/AD5	Ethernet controller address/data bus, bit 5
P60	CP2201/AD6	Ethernet controller address/date bus, bit 6
P61	CP2201/AD7	Ethernet controller address/date bus, bit 7
P62	No connection
P63	DGND
P64	No connection
P65	No connection
P66	+1.2V
P67	+3.3V
P68	+3.3V
P69	DGND
P70	ID3	Backplane location identifier jumper, pins 3 & 4 Active-low, FPGA should pull high
P71	ID2	Backplane location identifier jumper, pins 5 & 6 Active-low, FPGA should pull high
P72	ID1	Backplane location identifier jumper, pins 7 & 8 Active-low, FPGA should pull high
P73	ID0	Backplane location identifier jumper, pins 9 & 10 Active-low, FPGA should pull high
P74	DGND
P75	FPGA/TDO	JTAG
P76	FPGA/TCK	JTAG
P77	ID4	Backplane location identifier jumper, pins 1 & 2 Active-low, FPGA should pull high
P78	No connection
P79	+3.3V
P80	DGND
P81	+1.2V
P82	No connection
P83	CLK_5MHZ_2	5 MHz clock output for DAC
P84	No connection
P85	AD5535/DIN	DAC serial data input (FPGA out -> DAC in)
P86	No connection
P87	DGND
P89	No connection
P90	No connection
P91	DGND
P92	+3.3V
P93	AD7314/CE	Chip enable for temperature sensor
P94	No connection
P95	DGND
P96	+3.3V
P97	AD7928/DOUT	Erroneously wired ADC SPI bus connection Connects to DOUT on ADC
P98	AD5535/RESET	Reset pin for DAC
P99	DGND
P100	FPGA/PROG_B	Used during FPGA configuration - see Xilinx documentation

EEPROM

To facilitate power-on configuration of the FPGA, the control board includes a Xilinx XCF01S EEPROM. The EEPROM is located to the left of the FPGA, above the JTAG header, and has a 20 pin footprint. The EEPROM is labelled U5.

Power Details

The EEPROM uses +3.3V exclusively, which it receives from the +3.3V power plane, regulated by VR1.

Flashing/Burning/Writing

Whatever you call it, this refers to storing data in the EEPROM so that it can configure the FPGA at power-on. The EEPROM is programmed using a JTAG interface and the Xilinx Platform USB II cable. It is important to note that in digital board's JTAG chain, the EEPROM is the first device in the chain, unlike in the Xilinx documentation where it is shown as the second device. This should not affect the operation of the board, but should be reflected in the Xilinx software when writing the EEPROM via JTAG.

FPGA Configuration

The EEPROM and FPGA are hardwired to use a master serial protocol to transfer the program from the EEPROM to the FPGA. This is the protocol recommended in the Xilinx documentation because it minimizes the number of traces necessary to run between the EEPROM and FPGA. All configuration data is sent over a single trace, FPGA/DIN (pin 1 on EEPROM), controlled by the configuration clock signal (FPGA/CCLK) which is automatically generated by the FPGA at power-on. When configuration is complete, FPGA/DONE (pin 10) is pulled high by the FPGA, and the EEPROM and configuration clock are deactivated.

Pinout Table

Pin #	Net Name	Description
1	FPGA/DIN	Serial data line Carries data from the EEPROM to the FPGA
2	No connection
3	FPGA/CCLK	Configuration clock Auto generated by FPGA at power-on, disabled at end of configuration
4	EEPROM/TDI	This is the EEPROM's TDI This is the entry point for the onboard JTAG chain
5	FPGA/TMS	JTAG TMS Connects to both FPGA and EEPROM
6	FPGA/TCK	JTAG TCK Connects to both FPGA and EEPROM
7	FPGA/PROG_B	Used during configuration See Xilinx documentation
8	FPGA/INIT_B	Used during configuration - can be used to intiate reconfiguration of FPGA See Xilinx documentation
9	No connection
10	FPGA/DONE	Indicates completion of FPGA configuration High when complete
11	DGND
12-16	No connection
17	FPGA/TDI	This is the EEPROM's TDO/FPGA's TDI
18-20	+3.3V

JTAG Header

To write the FPGA's program to the EEPROM, the board employs a JTAG based programming system consistent with Xilinx's recommendations. The system is designed to operate with Xilnx's Platform USB II cable and the flying lead adapter.

Header Location and Size

The header consists of 14 pins, 100 mil pitch, just below the EEPROM (U5). The header is labelled P1. The pitch of the pins in the header was erroneously selected to be 100 mil, which is not compatible with Xilinx's JTAG ribbon cable. Therefore, the Xilinx flying lead adapter must be used.

Power Details

The JTAG interface is powered by the +3.3V power plane, not by the computer's USB port. Power is supplied through pin 2 of the JTAG header.

Pinout Table

Note that the header is positioned on the board rotated 180 degrees from the position in which it is shown in the Xilinx documentation. Care must be taken when connecting the flying leads to ensure they are connected to the right pins. Connecting the flying leads to the wrong side of the header will cause all of the leads to short on the digital board's ground plane. This will certainly cause undesired operation, and may or may not cause damage. Improper wiring is most likely to cause damage if one of the flying leads is connected to an odd numbered pin. Note from the pinout table below that no flying lead connections should ever be made to the odd numbered pins on the JTAG header.

Pin #	Net Name	Description
1, 3, 5, 7, 9, 11, 13 (odd pins)	DGND	Ground pins for signal integrity Never connect a flying lead to these pins Doing so will short to ground and may cause permanent damage if the Platform USB II cable does not have protection against this.
2	+3.3V	Power source for all JTAG logic
4	FPGA/TMS	JTAG TMS - connects to EEPROM and FPGA
6	FPGA/TCK	JTAG TCK - connects to EEPROM and FPGA
8	FPGA/TDO	JTAG boundary scan chain endpoint
10	EEPROM/TDI	JTAG boundary scan chain start point
12	No connection	Pin is floating
14	No connection	Pin is floating

JTAG Overview

The JTAG interface is clocked by the TCK signal. TCK is generated by the Platform USB II cable, and connects directly from the JTAG header to both the EEPROM and FPGA.

The TMS signal is directly connected to both the EEPROM and FPGA, and is the data line over which JTAG test results (in this case programming results) are sent. TMS is used by only one component at a time.

The TDI/TDO lines form a chain that connects to each JTAG component in series. On the control board, the first point in the chain is the EEPROM's TDI. Next is the EEPROM's TDO, which is the same as the FPGA's TDI. The FPGA's TDO then returns to the JTAG header and the Platform USB II cable.

DAC

The control board uses the Analog Devices AD5535, 32-channel, 200V max, digital to analog converter. This chip has a modified BC-124 BGA footprint and is located above the Eurocard connector at the bottom of the board. It is labelled U3.

Power Details

The DAC is primarily powered by the +5V power island, regulated by an off-board power supply and extensively decoupled in the area of the DAC. The DAC also requires -5V, and a high voltage as discussed in Power Requirements. Both of these voltages are supplied by an off-board supply and decoupled near the DAC. In addition to these voltage levels, the DAC requires a precise +2.5V reference, created by the shunt-type voltage reference VR4.

Setting the Output Range

The output range of the DAC is set by the 2.5V reference voltage supplied by VR4. The high voltage power supply must supply at a minimum 50 times this voltage, plus 10. Thus, the high voltage power supply should be at least 135V for DAC to operate properly, even though the SiPMs are expected to need only 40V. If it is convenient to use a lower high voltage, VR4 must be replaced to provide lower reference voltage. The high voltage may then be decreased appropriately. To summarize:

• Max output voltage = VREF*50
• Minimum high voltage supply = VREF*50 + 10
• Acceptable range for VREF
  • Min: 1V
  • Max: 3.75V (AD5535 datasheet specifies 4V max, but this would require AVCC of 5.25V for the DAC, which is not possible in the current board design)

If relevant, R13 is a 100K resistor.

Thermal Diode

The DAC has a built in thermal diode. The diode drop from anode to cathode is typically 0.65V at 25°C. It changes at a rate of -2.20mV/°C. The anode of this diode is connected to the +5V power island, and the cathode is connected to a 270K resistor to ground. The voltage between the cathode and the resistor is connected to VIN1 (pin 15) on the ADC).

Pinout Table

See documentation from Analog Devices.

Channel Mapping

Due to the layout of the balls on the footprint of the DAC, the DAC's internal channel numbers (which must be referenced by the FPGA) have no correlation to the channel numbers on the amplifier board. This table summarizes the mapping between various pins that belong to each channel.

DAC Channel #	DAC Pin #	Digital Board Eurocard Pin #	Amplifier Board Eurocard Pin #	Physical Channel #
0	B1	B3
1	A2	C4
2	D1	B2
3	C2	C3
4	B3	B4
5	E2	C2
6	F3	B1
7	A4	B5
8	E4	C5
9	B5	C6
10	F5	C1
11	A6	C7
12	E6	B6
13	B7	B7
14	F7	C10
15	E8	C8
16	A8	B8
17	B9	C9
18	F9	C16
19	E10	B11
20	A10	B9
21	B11	B10
22	C12	B12
23	D13	B13
24	E12	B14
25	A12	C11
26	B13	C12
27	H13	B16
28	G14	B15
29	C14	C13
30	F13	C15
31	E14	C14		DACHEALTH... anything else??