Difference between revisions of "Digital control board documentation"

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(thru P44)
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−
=== Power Sequencing ===
+
=== Power Supply Sequencing ===
−
The control board is designed such that voltages may be supplied in any order so long as the grounds are connected properly.  However, for initial testing, the preferred order for powering up the board should be as follows:
+
The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly.  However, for initial testing, the preferred order for powering up the board is as follows:
  
 
# Ensure AGND/DGND are connected/grounded
 
# Ensure AGND/DGND are connected/grounded
Line 34: Line 34:
 
# -5V
 
# -5V
 
# High voltage
 
# High voltage
 +
 +
== FPGA ==
 +
The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.
 +
 +
=== Power Details ===
 +
The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.
 +
 +
=== Logic Standard ===
 +
The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a '''3.3V CMOS''' logic standard.
 +
 +
=== Pinout Table ===
 +
{| cellpadding=3 border=1 |
 +
| '''Pin #'''
 +
| '''Net Name'''
 +
| '''Description'''
 +
|-
 +
| P1
 +
| FPGA/TMS
 +
| JTAG
 +
|-
 +
| P2
 +
| FPGA/TDI
 +
| JTAG
 +
|-
 +
| P3
 +
| AD7928/CS
 +
| SPI chip select for ADC
 +
|-
 +
| P4
 +
| SPI
 +
| '''Erroneously wired SPI bus trace... see notes below (coming soon)'''
 +
|-
 +
| P5
 +
| CLK_5MHZ
 +
| 5 MHz clock output for SPI bus (ADC and temp. sensor)
 +
|-
 +
| P6
 +
| No connection
 +
|
 +
|-
 +
| P7
 +
| No connection
 +
|
 +
|-
 +
| P8
 +
| DGND
 +
|
 +
|-
 +
| P9
 +
| No connection
 +
|
 +
|-
 +
| P10
 +
| No connection
 +
|
 +
|-
 +
| P11
 +
| +3.3V
 +
|
 +
|-
 +
| P12
 +
| No connection
 +
|
 +
|-
 +
| P13
 +
| No connection
 +
|
 +
|-
 +
| P14
 +
| DGND
 +
|
 +
|-
 +
| P15
 +
| No connection
 +
|
 +
|-
 +
| P16
 +
| No connection
 +
|
 +
|-
 +
| P17
 +
| +1.2V
 +
|
 +
|-
 +
| P18
 +
| DGND
 +
|
 +
|-
 +
| P19
 +
| No connection
 +
|
 +
|-
 +
| P20
 +
| No connection
 +
|
 +
|-
 +
| P21
 +
| No connection
 +
|
 +
|-
 +
| P22
 +
| +3.3V
 +
|
 +
|-
 +
| P23
 +
| DGND
 +
|
 +
|-
 +
| P24
 +
| DGND
 +
|
 +
|-
 +
| P25
 +
| DGND
 +
|
 +
|-
 +
| P26
 +
| +3.3V
 +
|
 +
|-
 +
| P27
 +
| FPGA/CLK_IN
 +
| 20 MHz clock input from crystal oscillator
 +
|-
 +
| P28
 +
| No connection
 +
|
 +
|-
 +
| P29
 +
| No connection
 +
|
 +
|-
 +
| P30
 +
| No connection
 +
|
 +
|-
 +
| P31
 +
| No connection
 +
|
 +
|-
 +
| P32
 +
| No connection
 +
|
 +
|-
 +
| P33
 +
| No connection
 +
|
 +
|-
 +
| P34
 +
| No connection
 +
|
 +
|-
 +
| P35
 +
| CP2201/INT
 +
| Ethernet controller interrupt
 +
|-
 +
| P36
 +
| MASTER_RESET
 +
| Connects to RESET jumper in upper left of board (active-low, externally pulled up)
 +
|-
 +
| P37
 +
| No connection
 +
|
 +
|-
 +
| P38
 +
| +1.2V
 +
|
 +
|-
 +
| P39
 +
| No connection
 +
|
 +
|-
 +
| P40
 +
| CP2201/CS
 +
| Chip select for ethernet controller
 +
|-
 +
| P41
 +
| CP2201/WR
 +
| Write enable for ethernet controller
 +
|-
 +
| P42
 +
| DGND
 +
|
 +
|-
 +
| P43
 +
| CP2201/RD
 +
| Read enable for ethernet controller
 +
|-
 +
| P44
 +
| CP2201/ALE
 +
| Address line enable for ethernet controller
 +
|}

Revision as of 18:07, 11 June 2009

This documentation covers the most important things to know while testing the digital control board, including component pinouts, nets, and other information.

Power Requirements

Required Voltages

All components on the digital board except the DAC can be tested using only a +5V source. The DAC requires +5V, -5V, and a high voltage corresponding to 10V higher than the maximum desired DAC output voltage. Digital and analog grounds must be connected as well before any testing takes place.

Power Pins

Power shall be connected to the board as follows:

Voltage Eurocard Pin
DGND A6
AGND A5
+5V A4
-5V A3
High voltage
(DAC max out +10,
not to exceed +210V) 		A2

Power Supply Sequencing

The control board is designed such that voltages may be supplied in any order so long as AGND and DGND are connected properly. However, for initial testing, the preferred order for powering up the board is as follows:

  1. Ensure AGND/DGND are connected/grounded
  2. +5V
  3. -5V
  4. High voltage

FPGA

The control board uses a Xilinx XC3S50A VQ100 FPGA. It has a 100 pin footprint and is located in the center of the control board.

Power Details

The FPGA is powered by the 3.3V power plane, which is regulated by VR1. The FPGA also obtains 1.2V for its internal logic from a 1.2V power island, regulated by VR3.

Logic Standard

The Xilinx XC3S50A supports several different digital logic standards. The control board is hard wired such that the FPGA will use a 3.3V CMOS logic standard.

Pinout Table

Pin # Net Name Description
P1 FPGA/TMS JTAG
P2 FPGA/TDI JTAG
P3 AD7928/CS SPI chip select for ADC
P4 SPI Erroneously wired SPI bus trace... see notes below (coming soon)
P5 CLK_5MHZ 5 MHz clock output for SPI bus (ADC and temp. sensor)
P6 No connection
P7 No connection
P8 DGND
P9 No connection
P10 No connection
P11 +3.3V
P12 No connection
P13 No connection
P14 DGND
P15 No connection
P16 No connection
P17 +1.2V
P18 DGND
P19 No connection
P20 No connection
P21 No connection
P22 +3.3V
P23 DGND
P24 DGND
P25 DGND
P26 +3.3V
P27 FPGA/CLK_IN 20 MHz clock input from crystal oscillator
P28 No connection
P29 No connection
P30 No connection
P31 No connection
P32 No connection
P33 No connection
P34 No connection
P35 CP2201/INT Ethernet controller interrupt
P36 MASTER_RESET Connects to RESET jumper in upper left of board (active-low, externally pulled up)
P37 No connection
P38 +1.2V
P39 No connection
P40 CP2201/CS Chip select for ethernet controller
P41 CP2201/WR Write enable for ethernet controller
P42 DGND
P43 CP2201/RD Read enable for ethernet controller
P44 CP2201/ALE Address line enable for ethernet controller
Retrieved from "https://zeus.phys.uconn.edu/wiki/index.php?title=Digital_control_board_documentation&oldid=4342"