Line 1: |
Line 1: |
− | = Registers = | + | === State Register === |
| | | |
− | === State Register ===
| |
| A three-bit register to store the current state. | | A three-bit register to store the current state. |
| + | |
| inputs | | inputs |
| * ''Clk'': clock | | * ''Clk'': clock |
− | * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) | + | * ''Rst'': asynchronous, reset to zero the register (puts system into reset state) |
| * ''En'': write enable | | * ''En'': write enable |
| * ''D'': three-bit data-in bus | | * ''D'': three-bit data-in bus |
Line 13: |
Line 13: |
| | | |
| | | |
− | === Packet Type Register === | + | === MAC Address Registers === |
− | An 8-bit register to store the 2nd byte of an accepted packet.
| + | |
| + | A set of 12 8-bit registers to store the board's and PC's MAC addresses (in that order). Note that all bits of the register are set high upon reset as a simple way to ensure that packets sent to the PC before its address has been learned will be interpreted as a broadcast packet. |
| + | |
| + | inputs |
| * ''Clk'': clock | | * ''Clk'': clock |
− | * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) | + | * ''Rst'': asynchronous reset to zero the register |
| * ''En'': write enable | | * ''En'': write enable |
− | * ''D'': 8-bit data-in bus | + | * ''A'': 3-bit address |
| + | * ''D'': 12-bit data-in bus |
| | | |
| outputs | | outputs |
− | * ''Q'': 8-bit data-out bus | + | * ''Q'': 16-bit data-out bus (data pre-padded with 4 zeros to facilitate packaging into 2-byte words) |
| | | |
| | | |
| === Temperature Register === | | === Temperature Register === |
− | A 16-bit register to store the most recent temperature data. | + | |
| + | A 10-bit register to store the most recent temperature data. A 16-bit word is actually returned for the convenience of other modules - the 10-bit value is pre-padded with zeros. |
| + | |
| inputs | | inputs |
| * ''Clk'': clock | | * ''Clk'': clock |
− | * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) | + | * ''Rst'': asynchronous reset to zero the register |
| * ''En'': write enable | | * ''En'': write enable |
| * ''D'': 10-bit data-in bus | | * ''D'': 10-bit data-in bus |
Line 37: |
Line 43: |
| | | |
| === ADC Registers === | | === ADC Registers === |
− | A set of eight 16-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. | + | |
| + | A set of eight 12-bit registers to store the most recent ADC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 12-bit data is pre-padded with zeros for the convenience of other modules. |
| + | |
| inputs | | inputs |
| * ''Clk'': clock | | * ''Clk'': clock |
− | * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) | + | * ''Rst'': asynchronous reset to zero the register |
| * ''En'': write enable | | * ''En'': write enable |
| * ''A'': 3-bit address | | * ''A'': 3-bit address |
Line 50: |
Line 58: |
| | | |
| === DAC Registers === | | === DAC Registers === |
− | A set of 32/24/16 16-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. | + | |
| + | A set of 32 14-bit registers to store the most recent DAC data. Also includes a demultiplexer to select which register to write to. In practice there is a 16-bit-wide bus on output: the 14-bit data is pre-padded with zeros for the convenience of other modules. |
| + | |
| inputs | | inputs |
| * ''Clk'': clock | | * ''Clk'': clock |
− | * ''/Rst'': asynchronous, active-low reset to zero the register (puts system into reset state) | + | * ''Rst'': asynchronous reset to zero the register |
| * ''En'': write enable | | * ''En'': write enable |
− | * ''A'': 5/5/4-bit address (currently set at 5-bit) | + | * ''A'': 5-bit address |
| * ''D'': 14-bit data-in bus | | * ''D'': 14-bit data-in bus |
| | | |
| outputs | | outputs |
| * ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words) | | * ''Q'': 16-bit data-out bus (data pre-padded with 2 zeros to facilitate packaging into 2-byte words) |