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SiPM digital control board netlist (view source)
Revision as of 15:47, 26 June 2008
, 15:47, 26 June 2008→Configuration Pins: removed EEPROM isolating logic information
== Overview ==
== Overview ==
This page contains a listing of the pins of all major ICs that will be used in the SiPM digital control board, sorted by what they will be connected to. This list is mostly complete, but will be expanded and corrected as the project progresses.
This page contains a listing of the pins of all major ICs that will be used in the SiPM digital control board, sorted by what they will be connected to. This list is mostly complete, but will be expanded and corrected as the project progresses.
To see connections in reference to available power supply voltages, see [[SiPM digital control board power supplies]].
== Legend ==
== Legend ==
The following table describes the ICs as they are referenced on this page.
The following table describes the ICs as they are referenced on this page. Clicking a component name will bring you to the component's datasheet.
{| cellpadding=3 border=1 |
{| cellpadding=3 border=1 |
|'''IC Name'''
|'''IC Name'''
|'''Description'''
|'''Description'''
|----
|----
|AD7928
|[http://www.analog.com/UploadedFiles/Data_Sheets/AD7908_7918_7928.pdf AD7928]
|8-bit analog-to-digital converter
|8 channel analog-to-digital converter
|----
|----
|AD5535
|[http://www.analog.com/UploadedFiles/Data_Sheets/AD5535.pdf AD5535]
|32 channel digital to analog converter
|32 channel digital-to-analog converter
|----
|----
|AD7314
|[http://www.analog.com/UploadedFiles/Data_Sheets/AD7314.pdf AD7314]
|10-bit temperature sensor
|10-bit temperature sensor
|----
|----
|CP2201
|[http://www.silabs.com/public/documents/tpub_doc/dsheet/Microcontrollers/Interface/en/CP2200.pdf CP2201]
|Ethernet controller
| Ethernet controller
|----
|[http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf XCF01S]
|[http://www.xilinx.com/products/silicon_solutions/proms/pfp/spartan.htm Xilinx Platform Flash EEPROM], Model XCF01S
|----
|----
|FPGA
|[http://www.xilinx.com/support/documentation/data_sheets/ds529.pdf XC3S50A]
|Xilinx Spartan-3A field programmable gate array
|Xilinx Spartan-3A field programmable gate array (FPGA)
|}
|}
This section defines some pins that must be on the FPGA, and what they must connect to. Many of these connections may also be found in the [[#IC netlist|IC netlist]].
This section defines some pins that must be on the FPGA, and what they must connect to. Many of these connections may also be found in the [[#IC netlist|IC netlist]].
=== Custom I/O pins ===
=== User I/O pins ===
For these I/O pins, "Pin Name" defines the name of the pins as they will be used for our project, not the actual pin name in the FPGA schematic.
For these I/O pins, "Pin Name" defines the name of the pins as they will be used for our project, not the actual pin name in the FPGA schematic. The physical FPGA pins used for each of these connections will be determined later to optimize the circuitry around the FPGA.
{| cellpadding=3 border=1 |
{| cellpadding=3 border=1 |
|Input from temperature sensor
|Input from temperature sensor
|AD7314 pin 5
|AD7314 pin 5
|----
|----
|DAC_OUT
|DAC_OUT
=== Configuration Pins ===
=== Configuration Pins ===
These pins are used for the programming of the FPGA.
These pins are used for the programming of the FPGA. Many of these pins revert to user I/O pins after programming is complete.
We will be using the master serial (Platform Flash) programming mode (see [[FPGA programming modes]]). Configuration pins not used in this mode are omitted from the table below. The connections that are in the table are also visually described on page 16 of the [http://www.xilinx.com/support/documentation/data_sheets/ds123.pdf XCF01S data sheet].
{| cellspacing=3 border=1 |
{| cellspacing=3 border=1 |
|'''Pin Name'''
|'''Pin Name'''
|'''Description'''
|'''Description'''
|'''Connect To'''
|'''During Programming<br>Connect To'''
|'''After Programming<br>Connect To'''
|'''Notes'''
|'''Notes'''
|---
|---
|M0
|M0
|Mode select pin for configuration
|Mode select pin for configuration
|FPGA programmer
|Ground
| rowspan=3 | See [[FPGA programming modes]]
|User I/O
| rowspan=3 | Should be <0:0:0> during configuration to indicate master serial mode
See [[FPGA programming modes]]
|----
|----
|M1
|M1
|Mode select pin for configuration
|Mode select pin for configuration
|FPGA programmer
|Ground
|User I/O
|----
|----
|M2
|M2
|Mode select pin for configuration
|Mode select pin for configuration
|FPGA programmer
|Ground
|User I/O
|----
|----
|DONE
|DONE
|Programming complete pin
|Programming complete pin
|FPGA programmer?
|XCF01S CE, pin 10
|XCF01S CE, pin 10
|Goes high when programming is complete
|Goes high when programming is complete
|----
|----
|PROG_B
|PROG_B
|Initiates programming process
|Initiates programming process
|FPGA programmer
|XCF01S CF, pin 7
|XCF01S CF, pin 7
|Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation
|Low causes master reset of FPGA<br>High initiates programming after reset<br>Should be high for normal operation
|----
|----
|CCLK
|CCLK
|Clock for programming
|Clock for programming
|FPGA programmer?
|XCF01S CLK, pin 3
|User I/O
|If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input
|If M[2:0] define a master mode, CCLK is internally generated<br>If M[2:0] define a slave mode, CCLK is a clock input
|----
|----
|INIT_B
|INIT_B
|Programming status indicator
|Programming status indicator
|FPGA programmer
|XCF01S OE/RESET, pin 8
|Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error
|User I/O, or high or low
|Before programming, low indicates internal memory is being cleared<br>During programming, low indicates CRC error<br>After programming, should be driven high or <br>low if not used for user I/O
|----
|PUDC_B
|User I/O pull-up control
|???
|User I/O
|Set low during programming to enable pull-ups on all user I/O pins<br>after configuration
|----
|DIN
|Serial data input
|XCF01S D0, pin 1
|User I/O
|Serial data input from XCF01S
|----
|DOUT
|Serial data output
|''No connection''
|User I/O
|Used to daisy chain to next FPGA, if this were a multi-FPGA design<br>We are using only one FPGA per PCB, so this is not used
|----
|----
|}
|}
|N3
|N3
|CATHODE
|CATHODE
|???
|AD7928 Vin6 and resistor to ground
|Cathode of internal diode for temperature monitoring
|Cathode of internal diode for temperature monitoring
|----
|----
|N4
|N4
|ANODE
|ANODE
|???
| +3.3V rail
|Anode of internal diode for temperature monitoring
|Anode of internal diode for temperature monitoring
|----
|----
|19
|19
|VDRIVE
|VDRIVE
|Power supply, ???V
|Power supply, 3.3V
|Sets voltage at which DOUT operates
|Sets voltage at which DOUT operates
|----
|----
|16
|16
|Vin0
|Vin0
|Voltage input
| +1.2V rail
|Voltage being measured by ADC
| rowspan=5 | See [[SiPM digital control board power supplies]]
|----
|----
|AD7928
|AD7928
|15
|15
|Vin1
|Vin1
|Voltage input
| +2.5V rail
|----
|----
|AD7928
|AD7928
|14
|14
|Vin2
|Vin2
|Voltage input
| +3.3V rail
|----
|----
|AD7928
|AD7928
|13
|13
|Vin3
|Vin3
|Voltage input
| +5V rail
|----
|----
|AD7928
|AD7928
|12
|12
|Vin4
|Vin4
|Voltage input
| -5V rail
|----
|----
|AD7928
|AD7928
|11
|11
|Vin5
|Vin5
|Voltage input
| Cathode of AD5535 temperature diode
|Voltage being measured by ADC
|
|----
|----
|AD7928
|AD7928
|10
|10
|Vin6
|Vin6
|Voltage input
| ???
|Voltage being measured by ADC
| Should be used for any other voltage that must be monitored
|----
|----
|AD7928
|AD7928
|9
|9
|Vin7
|Vin7
|Voltage input
| ???
|Voltage being measured by ADC
| Should be used for any other voltage that must be monitored
|----
|----
|CP2201
|CP2201